公开(公告)号：US20110068423A1

公开(公告)日：2011-03-24

申请号：US12562362

申请日：2009-09-18

申请人： John M. Aitken

发明人： John M. Aitken

IPC分类号： H01L31/14 ,  G06F17/50 ,  H01L31/18 ,  H01L31/0232

CPC分类号： H01L31/0232 ,  G02B6/421

摘要： The disclosure relates generally to photodetectors and methods of forming the same, and more particularly to optical photodetectors. The photodetector includes a waveguide having a radius that controls the specific wavelength or specific range of wavelengths being detected. The disclosure also relates to a design structure of the aforementioned.

摘要翻译： 本公开一般涉及光电探测器及其形成方法，更具体地涉及光电探测器。 光电检测器包括具有控制要检测的特定波长或特定波长范围的半径的波导。 本公开还涉及上述的设计结构。

公开(公告)号：US07715248B2

公开(公告)日：2010-05-11

申请号：US12109081

申请日：2008-04-24

申请人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

发明人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC分类号： G11C7/00 ,  G11C7/22

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

摘要翻译： 本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。 具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。 读写电路和操作也在本申请中提供。

公开(公告)号：US07084483B2

公开(公告)日：2006-08-01

申请号：US10709727

申请日：2004-05-25

申请人： John M. Aitken ,  Fen Chen ,  Timothy D. Sullivan

发明人： John M. Aitken ,  Fen Chen ,  Timothy D. Sullivan

IPC分类号： H01L29/00

CPC分类号： H01L28/20 ,  H01L27/101

摘要： An on-chip, ultra-compact, and programmable semiconductor resistor device and device structure and a method of fabrication. Each semiconductor resistor device structure is formed of one or more conductively connected buried trench type resistor elements exhibiting a precise resistor value. At least two semiconductor resistor device structures may be connected in series or in parallel configuration through the intermediary of one or more fuse devices that may be blown to achieve a desired total resistance value.

公开(公告)号：US06252275B1

公开(公告)日：2001-06-26

申请号：US09226677

申请日：1999-01-07

申请人： John M. Aitken ,  Steven W. Mittl ,  Alvin W. Strong

发明人： John M. Aitken ,  Steven W. Mittl ,  Alvin W. Strong

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7881

摘要： A non-volatile random access memory (NVRAM) structure comprising an injector element in a single crystal silicon substrate; an insulator layer over the substrate; a silicon-on-insulator (SOI) layer over the insulator layer; and a sensing element in the SOI layer overlying the injector element. The NVRAM structure may further comprise a gate above the SOI layer, a floating gate in the insulator layer, or both.

摘要翻译： 一种非易失性随机存取存储器（NVRAM）结构，其包括在单晶硅衬底中的注入元件; 衬底上的绝缘体层; 在绝缘体层上的绝缘体上硅（SOI）层; 以及覆盖注射器元件的SOI层中的感测元件。 NVRAM结构还可以包括在SOI层上方的栅极，绝缘体层中的浮动栅极或两者。

公开(公告)号：US07935609B2

公开(公告)日：2011-05-03

申请号：US12186750

申请日：2008-08-06

申请人： John M. Aitken ,  Ethan H. Cannon

发明人： John M. Aitken ,  Ethan H. Cannon

IPC分类号： H01L21/76

CPC分类号： H01L27/0688 ,  H01L21/2007 ,  H01L21/76264 ,  H01L21/8221 ,  H01L21/84

摘要： A method is provided for fabricating a semiconductor device and more particularly to a method of manufacturing a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The method includes removing a substrate from an SOI wafer and selectively removing a buried oxide layer formed as a layer between the SOI wafer and active regions of a device. The method further comprises selectively removing isolation oxide formed between the active regions, and replacing the removed buried oxide layer and the isolation oxide with radiation hardened insulators.

摘要翻译： 提供一种用于制造半导体器件的方法，更具体地说，涉及在SOI技术中制造具有辐射硬化掩埋绝缘体和隔离绝缘体的半导体器件的方法。 该方法包括从SOI晶片去除衬底并选择性地去除在SOI晶片和器件的有源区之间形成为层的掩埋氧化物层。 该方法还包括选择性地去除在有源区之间形成的隔离氧化物，并用辐射硬化绝缘体代替去除的掩埋氧化物层和隔离氧化物。

公开(公告)号：US07736915B2

公开(公告)日：2010-06-15

申请号：US11276248

申请日：2006-02-21

申请人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

发明人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

IPC分类号： H01L21/00 ,  H01L31/00 ,  H01L31/0248 ,  H01L31/0352

CPC分类号： H01L21/743 ,  H01L21/76275

摘要： A method for neutralizing trapped charges in a buried oxide layer. The method includes providing a semiconductor structure which includes (a) a semiconductor layer, (b) a charge accumulation layer on top of the semiconductor layer, and (c) a doped region in direct physical contact with the semiconductor layer, wherein the charge accumulation layer comprises trapped charges of a first sign, and wherein the doped region and the semiconductor layer form a P-N junction diode. Next, free charges are generated in the P-N junction diode, wherein the free charges are of a second sign opposite to the first sign. Next, the free charges are accelerated towards the charge accumulation layer, resulting in some of the free charges entering the charge accumulation layer and neutralizing some of the trapped charges in the charge accumulation layer.

摘要翻译： 一种用于中和掩埋氧化物层中的俘获电荷的方法。 该方法包括提供半导体结构，该半导体结构包括（a）半导体层，（b）半导体层顶部的电荷累积层，和（c）与该半导体层直接物理接触的掺杂区域，其中电荷累积 层包括第一符号的俘获电荷，并且其中所述掺杂区域和所述半导体层形成PN结二极管。 接下来，在P-N结二极管中产生自由电荷，其中自由电荷是与第一符号相反的第二符号。 接下来，免费电荷朝向电荷累积层加速，导致一些自由电荷进入电荷累积层并中和电荷累积层中的一些俘获电荷。

公开(公告)号：US20080232159A1

公开(公告)日：2008-09-25

申请号：US12109081

申请日：2008-04-24

申请人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

发明人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

公开(公告)号：US07315075B2

公开(公告)日：2008-01-01

申请号：US10905906

申请日：2005-01-26

申请人： John M Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

发明人： John M Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L27/1203 ,  H01L29/92

摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.

摘要翻译： 公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。 多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。 所形成的第一体层的隔离部分限定第一电容器板。 与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。 硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。 第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

公开(公告)号：US07064414B2

公开(公告)日：2006-06-20

申请号：US10904483

申请日：2004-11-12

申请人： John M Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

发明人： John M Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

IPC分类号： H01L29/00

CPC分类号： H01L24/80 ,  H01L23/345 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00

摘要： A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heating element is formed within the bulk layer. A first side of the first heating element is adjacent to a first portion of the insulator layer. The first heating element is adapted to be selectively activated to generate thermal energy to heat the first portion of the insulator layer and anneal a trapped electrical charge from the first portion of the insulator layer.

摘要翻译： 一种从半导体器件退火俘获电荷的结构和相关方法。 半导体结构包括基板和第一加热元件。 衬底包括体层，绝缘体层和器件层。 第一加热元件形成在本体层内。 第一加热元件的第一侧与绝缘体层的第一部分相邻。 第一加热元件适于被选择性地激活以产生热能来加热绝缘体层的第一部分并且从绝缘体层的第一部分退火被俘获的电荷。

公开(公告)号：US06352902B1

公开(公告)日：2002-03-05

申请号：US09616818

申请日：2000-07-13

申请人： John M. Aitken ,  Alvin W. Strong

发明人： John M. Aitken ,  Alvin W. Strong

IPC分类号： H01L2120

CPC分类号： H01L28/60 ,  H01L21/31116 ,  H01L21/76838 ,  H01L23/5222 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A trench capacitor for use with a substrate. The capacitor has an inner electrode formed above the substrate. The inner electrode has a plurality of metal layers, a dielectric partially surrounding the inner electrode, and an outer electrode partially surrounding the dielectric.

摘要翻译： 用于衬底的沟槽电容器。 电容器具有形成在基板上方的内电极。 内部电极具有多个金属层，部分地围绕内部电极的电介质和部分地围绕电介质的外部电极。