公开(公告)号：US08519507B2

公开(公告)日：2013-08-27

申请号：US12493616

申请日：2009-06-29

申请人： Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

发明人： Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

IPC分类号： H01L23/52

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

摘要翻译： 包括阳极接触区域和阴极接触区域的电可编程熔丝由其上形成有硅化物层的多晶硅层和导电连接阴极接触区域与阳极接触区域的熔丝链形成，该熔丝链可通过应用 编程电流，以及分别形成在阴极接触区域的硅化物层上或在阴极接触区域和阳极接触区域的硅化物层上以预定构造形成的多个不规则接触。

公开(公告)号：US08350264B2

公开(公告)日：2013-01-08

申请号：US12835764

申请日：2010-07-14

申请人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

发明人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

IPC分类号： H01L29/04

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region. In this way, the antifuse can be configured such that the application of a programming voltage between the anode and the cathode heats the first semiconductor region sufficiently to reach a temperature which drives a dopant outwardly therefrom, causing an edge of the first semiconductor region to move closer to an adjacent edge of the second semiconductor region, thus permanently reducing electrical resistance between the first and second semiconductor regions by one or more orders of magnitude.

摘要翻译： 提供一种具有单一单晶半导体本体的反熔丝，该单体半导体本体包括具有相同的第一导电类型的第一和第二半导体区域以及具有与第一导电类型相反的第二导电类型的第一和第二半导体区域之间的第三半导体区域。 阳极和阴极可以与第一半导体区域电连接。 包括金属，金属的导电化合物或金属的合金的导电区域可以接触第一半导体区域并在阴极和阳极之间延伸。 反熔丝还可以包括与第二半导体区域电连接的触点。 以这种方式，反熔丝可被配置为使得在阳极和阴极之间施加编程电压将第一半导体区域充分加热以达到从其向外驱动掺杂剂的温度，从而使第一半导体区域的边缘移动 更靠近第二半导体区域的相邻边缘，从而将第一和第二半导体区域之间的电阻永久地减小一个或多个数量级。

公开(公告)号：US07817455B2

公开(公告)日：2010-10-19

申请号：US12065202

申请日：2006-08-30

申请人： Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

发明人： Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/165 ,  G11C29/027

摘要： A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp, for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.

摘要翻译： 一次性可编程只读存储器（OTPROM）在二维阵列中实现，这些阵列具有大规模的自杀可迁移电子保险丝。 通过在VDD处工作的解码逻辑执行字线选择，同时位线驱动器在VDD和较高电压Vp之间切换，用于编程。 因此，OTPROM与其他技术兼容，并且可以与其他技术集成，而无需使用成本加法器，并支持在熔丝编程期间最小化电压降的高电流路径的优化。 具有可编程参考的差分读出放大器用于改进的检测余量，并且可以支持整个位线，而不是为各个保险丝提供感测放大器。

公开(公告)号：US20090321735A1

公开(公告)日：2009-12-31

申请号：US12555241

申请日：2009-09-08

申请人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

发明人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.

摘要翻译： 具有包括非硅化半导体材料区域的连接的反熔丝可以以降低的电压和电流进行编程，并且通过金属或硅化物从阴极电迁移到非硅化半导体材料的区域而减少产生热量，从而形成具有降低的体积电阻的合金 。 阴极和阳极优选成形为控制从哪里和哪些材料被电迁移的区域。 在编程之后，材料的额外电迁移可将反熔丝返回到高电阻状态。 反熔丝制造的过程与场效应晶体管的制造完全兼容，并且反熔丝可有利地形成在隔离结构上。

公开(公告)号：US20080316789A1

公开(公告)日：2008-12-25

申请号：US12065202

申请日：2006-08-30

申请人： Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

发明人： Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

IPC分类号： G11C17/00 ,  G11C17/16

CPC分类号： G11C17/16 ,  G11C17/165 ,  G11C29/027

摘要： A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.

摘要翻译： 一次性可编程只读存储器（OTPROM）在二维阵列中实现，这些阵列具有大规模的自杀可迁移电子保险丝。 字线选择通过在VDD处工作的解码逻辑进行，而位线驱动器在VDD和较高电压Vp之间切换，用于编程。 因此，OTPROM与其他技术兼容，并且可以与其他技术集成，而无需使用成本加法器，并支持在熔丝编程期间最小化电压降的高电流路径的优化。 具有可编程参考的差分读出放大器用于改进的检测余量，并且可以支持整个位线，而不是为各个保险丝提供感测放大器。

公开(公告)号：US20080218247A1

公开(公告)日：2008-09-11

申请号：US11683081

申请日：2007-03-07

申请人： Byeongju Park ,  John M. Safran

发明人： Byeongju Park ,  John M. Safran

IPC分类号： H01H37/76

CPC分类号： G11C17/18

摘要： The present invention provides a circuit for determining the optimal gate voltage for programming transistors. The determination of the optimal voltage compensates for the variations in the programming current due to process variations in manufacturing or due to ambient conditions. By applying the optimal gate voltage thus determined to the programming transistors of electrical fuses, the optimal level of current is passed through the electrical fuses to enable high yielding and reliable electrical fuse programming.

摘要翻译： 本发明提供一种用于确定编程晶体管的最佳栅极电压的电路。 最佳电压的确定补偿了由于制造过程变化或由于环境条件而导致的编程电流的变化。 通过将如此确定的最佳栅极电压施加到电熔丝的编程晶体管，最佳电流电流通过电熔丝，以实现高屈服和可靠的电熔丝编程。

公开(公告)号：US20080217658A1

公开(公告)日：2008-09-11

申请号：US11683075

申请日：2007-03-07

申请人： Deok-kee Kim ,  Hoki Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park ,  John M. Safran

发明人： Deok-kee Kim ,  Hoki Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park ,  John M. Safran

IPC分类号： H01L27/10 ,  H01L29/00

CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and then by inducing electromigration of the conducting material into the antifuse link, the resistance of the antifuse structure is changed. By providing a terminal on the antifuse link, the change in the electrical properties of the antifuse link is detected and sensed. Also disclosed are an integrated antifuse with a built-in sensing device and a two dimensional array of integrated antifuses that can share programming transistors and sensing circuitry.

摘要翻译： 本发明提供了利用电迁移进行编程的反熔丝的结构。 通过在没有导电材料的情况下提供具有高电阻的一部分反熔丝连接，然后通过将导电材料电迁移到反熔丝连接中，反熔丝结构的电阻改变。 通过在反熔丝链路上设置端子，检测和感测反熔丝连接的电特性的变化。 还公开了具有内置感测装置的集成反熔丝和可共享编程晶体管和感测电路的集成反熔丝的二维阵列。

公开(公告)号：US07139990B2

公开(公告)日：2006-11-21

申请号：US10807478

申请日：2004-03-23

申请人： Raminderpal Singh ,  Yue Tan ,  Jean-Oliver Plouchart ,  Lawrence F. Wagner, Jr. ,  Mohamed Talbi ,  John M. Safran ,  Kun Wu

发明人： Raminderpal Singh ,  Yue Tan ,  Jean-Oliver Plouchart ,  Lawrence F. Wagner, Jr. ,  Mohamed Talbi ,  John M. Safran ,  Kun Wu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5022

摘要： A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.

摘要翻译： 描述了一种基于子电路的提取方法，其直接提取多指状MOS晶体管作为子电路。 通过添加三个标记层，该方法为布局提取的网表提供了与基于子电路模型的示意图网表中所示的设备属性对应的设备几何参数的完整列表。 通过基于提取的所有几何参数执行布局与原理图比较，以完整和准确的方式执行布局检查，其中根据相应的设计原理图检查每个设备参数。 这种完整和准确的几何参数比较增强了布局物理验证的置信度。

公开(公告)号：US07723820B2

公开(公告)日：2010-05-25

申请号：US11616965

申请日：2006-12-28

申请人： Deok-kee Kim ,  Byeongju Park ,  John M. Safran

发明人： Deok-kee Kim ,  Byeongju Park ,  John M. Safran

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C17/18 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides structures for an integrated antifuse that incorporates an integrated sensing transistor with an integrated heater. Two terminals connected to the upper plate allow the heating of the upper plate, accelerating the breakdown of the antifuse dielectric at a lower bias voltage. Part of the upper plate also serves as the gate of the integrated sensing transistor. The antifuse dielectric serves as the gate dielectric of the integrated transistor. The lower plate comprises a channel, a drain, and a source of a transistor. While intact, the integrated sensing transistor allows a passage of transistor current through the drain. When programmed, the antifuse dielectric, which is the gate of the integrated transistor, is subjected to a gate breakdown, shorting the gate to the channel and resulting in a decreased drain current. The integrated antifuse structure can also be wired in an array to provide a compact OTP memory array.

摘要翻译： 本发明提供了一种集成反熔丝的结构，该结构集成了具有集成加热器的集成感测晶体管。 连接到上板的两个端子允许上板的加热，加速在更低偏压下的反熔丝电介质的击穿。 上板的一部分也用作集成感测晶体管的栅极。 反熔丝电介质用作集成晶体管的栅极电介质。 下板包括晶体管的沟道，漏极和源极。 虽然完整，集成感测晶体管允许晶体管电流通过漏极。 当编程时，作为集成晶体管的栅极的反熔丝电介质受到栅极击穿，使栅极短路到沟道并导致漏极电流降低。 集成的反熔丝结构也可以以阵列布线，以提供紧凑的OTP存储器阵列。

公开(公告)号：US07609577B2

公开(公告)日：2009-10-27

申请号：US11872273

申请日：2007-10-15

申请人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

发明人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027

摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus further including a latch device coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg, the latch device configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg; and the fuse and reference resistance legs further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.

摘要翻译： 在设计过程中使用的机器可读介质中体现的设计结构包括用于感测可编程电阻性存储元件装置的状态的装置，该装置还包括耦合到熔丝节点和参考节点的锁存装置，所述熔丝节点包括 所述锁存装置被配置为检测在所述参考节点和所述熔丝节点之间产生的差动信号，这是由于感测电流通过所述保险丝腿和所述参考电阻腿的结果; 并且熔丝和参考电阻腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流电平。