公开(公告)号：US5445985A

公开(公告)日：1995-08-29

申请号：US292521

申请日：1994-08-18

申请人： Joseph A. Calviello ,  John A. Pierro

发明人： Joseph A. Calviello ,  John A. Pierro

IPC分类号： H01L27/06 ,  H03G11/02 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/0605 ,  H03G11/025

摘要： Integrated circuit structure and processing is provided for a high power limiter including at least a first anti-parallel array of monolithically integrated Schottky diodes. In a further embodiment, integrated circuit structure and processing is provided for an MMIC, microwave and millimeter wave monolithic integrated circuit, including an amplifier and a high power limiter monolithically integrated on the same substrate.

摘要翻译： 提供了集成电路结构和处理，用于包括至少第一反并联阵列的单片集成肖特基二极管的高功率限制器。 在另一个实施例中，为MMIC，微波和毫米波单片集成电路提供集成电路结构和处理，其包括单片集成在同一衬底上的放大器和高功率限幅器。

公开(公告)号：US4724220A

公开(公告)日：1988-02-09

申请号：US817916

申请日：1986-01-10

申请人： Joseph A. Calviello

发明人： Joseph A. Calviello

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L29/08 ,  H01L29/812 ,  H01L21/265 ,  H01L21/302

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L29/0891 ,  H01L29/812 ,  H01L2924/0002 ,  Y10S148/053 ,  Y10S148/082 ,  Y10S148/088 ,  Y10S148/122

摘要： The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate in which two N layers for the drain electrodes and one N layer for the source electrode are formed in one of the semi-insulating surface. The N source electrode is centrally located between the two N electrodes and all three lie in the same plane. The source and drain electrodes are separated by a thin semi-insulating layer, the length of which can range from 0.5 micron to several micron range, depending on the desired voltage breakdown. A Schottky gate is defined in an active N layer directly above the source N layer. The ohmic contacts for the source and drain N layers are defined several microns away from the Schottky junction, resulting in a considerable improvement in device reliability. Reliability is further enhanced by the fact that the resulting device is buried within the material where it is insulated from the ambient.

摘要翻译： 描述了使用肖特基栅极结和用于源极和漏极的重掺杂N层的高性能和可靠的埋地沟道场效应晶体管（BCFET）的制造。 BCFET由半绝缘基板构成，其中在半绝缘表面之一上形成有用于漏电极的两个N层和用于源电极的一个N层。 N源电极位于两个N电极之间的中心，所有三个位于同一平面。 根据所需的电压击穿，源极和漏极由薄的半绝缘层分隔开，半绝缘层的长度可以在0.5微米到几微米的范围内。 在源N层正上方的有源N层中定义肖特基门。 用于源极和漏极N层的欧姆接触距离肖特基结约几微米，导致器件可靠性的显着提高。 通过将所得到的装置埋在材料中与绝缘材料绝缘的事实进一步增强了可靠性。

公开(公告)号：US4683642A

公开(公告)日：1987-08-04

申请号：US863797

申请日：1986-05-15

申请人： Joseph A. Calviello

发明人： Joseph A. Calviello

IPC分类号： H01L29/08 ,  H01L29/76 ,  H01L21/461 ,  H01L21/441 ,  H01L49/02

CPC分类号： H01L29/0895 ,  H01L29/7606 ,  Y10S438/957 ,  Y10T29/413

摘要： An MOMS tunnel emission transistor is provided by a plurality of mesa stacked horizontal layers including at least one semiconductor layer (63) having an exposed edge (68) at a generally vertical side (67) of the mesa, such as the 111 plane. A first metal layer (66) has a generally vertical portion (72) extending along the side of the mesa and forming a schottky junction with the edge of the semiconductor layer. A generally vertical oxide layer (70) is on the first metal layer, and a second metal layer (71) is on the oxide. The MOMS tunnel emission transistor is formed by metal (71) - oxide (70) - metal (66) - semiconductor (63).

摘要翻译： MOMS隧道发射晶体管由多个台面堆叠的水平层提供，包括至少一个半导体层（63），该半导体层在台面的大致垂直的侧面（67）（例如111平面）具有暴露的边缘（68）。 第一金属层（66）具有沿着台面的侧面延伸的大致垂直部分（72），并与半导体层的边缘形成肖特基结。 大致垂直的氧化物层（70）位于第一金属层上，第二金属层（71）位于氧化物上。 MOMS隧道发射晶体管由金属（71） - 氧化物（70） - 金属（66） - 半导体（63）形成。

公开(公告)号：US4075650A

公开(公告)日：1978-02-21

申请号：US675621

申请日：1976-04-09

申请人： Joseph A. Calviello

发明人： Joseph A. Calviello

IPC分类号： H01L21/316 ,  H01L23/31 ,  H01L23/482 ,  H01L29/47 ,  H01L29/861 ,  H01L29/864 ,  H01L29/48

CPC分类号： H01L21/31683 ,  H01L21/31654 ,  H01L23/3171 ,  H01L23/482 ,  H01L29/475 ,  H01L29/8613 ,  H01L29/864 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025

摘要： A mesa semiconductor device, including a metal film conductor located on the upper surface of the device about the base of the mesa to reduce skin effect loss.

公开(公告)号：US5159413A

公开(公告)日：1992-10-27

申请号：US625483

申请日：1990-12-11

申请人： Joseph A. Calviello ,  Grayce A. Hickman

发明人： Joseph A. Calviello ,  Grayce A. Hickman

IPC分类号： H01L21/20 ,  H01L21/84

CPC分类号： H01L27/18 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/84 ,  Y10S148/025 ,  Y10S148/072 ,  Y10S148/097 ,  Y10S505/703 ,  Y10S505/704

摘要： A semiconductor device and processing technique is provided for monolithic integration of a single crystal compound element semiconductor on a ceramic substrate. A high resistivity semi-insulating buffer layer is epitaxially grown on the ceramic substrate and has an elastically transitional lattice constant matching at its lower surface the lattice constant of the ceramic substrate, and matching at its upper surface the lattice constant of the semiconductor layer.

公开(公告)号：US4876176A

公开(公告)日：1989-10-24

申请号：US40416

申请日：1987-04-20

申请人： Joseph A. Calviello ,  Paul R. Bie ,  Ronald J. Pomian

发明人： Joseph A. Calviello ,  Paul R. Bie ,  Ronald J. Pomian

IPC分类号： G03F7/00 ,  H01L21/70 ,  H01L21/8252 ,  H01L27/06

CPC分类号： G03F7/00 ,  H01L21/707 ,  H01L21/8252 ,  H01L27/0605

摘要： Method for fabrication of quasi-monolithic microwave integrated circuits in which metals, oxides, and processes are selected to enable fabrication of the circuits by first producing many layers of metals and oxides in situ without removing the circuit from its environmental chamber. This reduces inclusion of contaminating chemical films and particles between the desired layers. Circuit elements are then defined by processing of the layers by photolithography and other processes from the top of the circuit downward. Lumped and distributed capacitors, resistors, inductors, transmission lines, and contacts for active devices are monolithically defined, with a reduced number of process steps.

摘要翻译： 制备准单片微波集成电路的方法，其中金属，氧化物和工艺被选择以通过首先在原位生产许多金属和氧化物而不从其环境室中除去电路来制造电路。 这减少了污染化学膜和颗粒在所需层之间的包含。 然后通过光刻和电路顶部的其它处理向下处理层来限定电路元件。 用于有源器件的集中和分布式电容器，电阻器，电感器，传输线和触点是单片定义的，并且具有减少的工艺步骤数量。

公开(公告)号：US4789645A

公开(公告)日：1988-12-06

申请号：US40418

申请日：1987-04-20

申请人： Joseph A. Calviello ,  Paul R. Bie ,  Ronald J. Pomian

发明人： Joseph A. Calviello ,  Paul R. Bie ,  Ronald J. Pomian

IPC分类号： H01L21/70 ,  H01L21/8252 ,  H01L29/48 ,  H01L21/283

CPC分类号： H01L21/707 ,  H01L21/8252 ,  Y10S148/014 ,  Y10S148/021 ,  Y10S438/913

摘要： During fabrication of monolithic microwave integrated circuits, active devices having sources, gates, drains, and/or Schottky barrier junctions are first provided for an epitaxial layers. Then many layers of metals and oxides are produced thereover in situ without removing the circuit from its environmental chamber. Circuit elements are then defined by processing of the many layers sequentially by photolithography and other processes from the top of the chip downward. Certain combinations of metals, oxides, and processes are selected to enable fabrication of circuits from the top down in this way. This reduces inclusion of contaminating chemical films and particles between the desired layers. Lumped and distributed capacitors, resistors, inductors, transmission lines, contacts, and complete active devices are monolithically defined, with a reduced number of process steps. An all-refractory MESFET is described, having a Schottky barrier gate and nonalloyed ohmic contacts for source and drain producible at room temperatures. Source, gate, and drain can be defined with a single mask. A thinner gold layer is formed for FET contacts than for other circuit conductors and elements by means of a configured tantalum layer buried in a thick gold layer.

摘要翻译： 在制造单片微波集成电路期间，首先提供具有源极，栅极，漏极和/或肖特基势垒结的有源器件用于外延层。 然后在原地生产许多层金属和氧化物，而不从其环境室中移除电路。 然后通过光刻和从芯片的顶部向下的其它处理顺序地处理许多层来定义电路元件。 选择金属，氧化物和工艺的某些组合以使得能够以这种方式从上到下制造电路。 这减少了污染化学膜和颗粒在所需层之间的包含。 集中和分布式电容器，电阻器，电感器，传输线，触点和完整的有源器件都是单片定义的，数量减少的工艺步骤。 描述了全难熔MESFET，其具有肖特基势垒栅极和用于在室温下可产生的源极和漏极的非合金欧姆接触。 源，栅极和漏极可以用单个掩模定义。 通过埋在厚金层中的配置的钽层，为FET触点形成更薄的金层，而不是其他电路导体和元件。

公开(公告)号：US4624004A

公开(公告)日：1986-11-18

申请号：US755534

申请日：1985-07-15

申请人： Joseph A. Calviello

发明人： Joseph A. Calviello

IPC分类号： H01L29/417 ,  H01L29/80 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L29/4175

摘要： The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate in which two N layers for the drain electrodes and one N layer for the source electrode are formed in one of the semi-insulating surface. The N source electrode is centrally located between the two N drain electrodes and all three lie in the same plane. The source and drain electrodes are separated by a thin semi-insulating layer, the length of which can range from 0.5 micron to several micron range, depending on the desired voltage breakdown. A Schottky gate is defined in an active N layer directly above the source N layer. The ohmic contacts for the source and drain N layers are defined several microns away from the Schottky junction, resulting in a considerable improvement in device reliability. Reliability is further enhanced by the fact that the resulting device is buried within the material where it is insulated from the ambient.

摘要翻译： 描述了使用肖特基栅极结和用于源极和漏极的重掺杂N层的高性能和可靠的埋地沟道场效应晶体管（BCFET）的制造。 BCFET由半绝缘基板构成，其中在半绝缘表面之一上形成有用于漏电极的两个N层和用于源电极的一个N层。 N源电极位于两个N个漏极之间的中心，所有三个位于同一平面。 根据所需的电压击穿，源极和漏极由薄的半绝缘层分隔开，半绝缘层的长度可以在0.5微米到几微米的范围内。 在源N层正上方的有源N层中定义肖特基门。 用于源极和漏极N层的欧姆接触距离肖特基结约几微米，导致器件可靠性的显着提高。 通过将所得到的装置埋在材料中与绝缘材料绝缘的事实进一步增强了可靠性。

公开(公告)号：US4549194A

公开(公告)日：1985-10-22

申请号：US365352

申请日：1982-03-29

申请人： Joseph A. Calviello

发明人： Joseph A. Calviello

IPC分类号： H01L31/0352 ,  H01L31/101 ,  H01L31/00

CPC分类号： H01L31/101 ,  H01L31/03529 ,  Y02E10/50

摘要： A tunnel diode having a generally rectangular junction area in the 10.sup.-10 to 10.sup.-11 cm.sup.2 range formed in a quasi-planar structure of a first metal, an oxide of the first metal and a second metal. The first metal may be tantalum or other similarly slow oxidizable metals. The second metal may be selected from a group also including tantalum. For a symmetrical junction, the first and second metals are the same, however, for an asymmetrical junction the first and second metals are different. To reduce the diode series electrical and thermal resistance, a gold layer is deposited over the first and second metals. The gold layer over the first metal is deposited everywhere except at or within a few microns of the junction. The device provides a small junction area and also negligible parasitic shunt capacitance which are necessary for efficient room temperature operation at frequencies in the submillimeter to optical region. Direct and heterodyne detection in the 10 microns region has been successfully achieved with these devices.

摘要翻译： 形成在第一金属，第一金属的氧化物和第二金属的准平面结构中的10-10至10-11cm 2范围内的大致矩形结面积的隧道二极管。 第一种金属可以是钽或其它类似的缓慢的可氧化金属。 第二金属可以选自也包括钽的组。 对于对称结，第一和第二金属是相同的，然而，对于非对称结，第一和第二金属是不同的。 为了降低二极管串联电阻和热阻，金层沉积在第一和第二金属上。 第一金属上的金层沉积在除了在该结的几微米处或其附近的任何地方。 该器件提供小的接合面积以及可忽略的寄生并联电容，这是在亚毫米至光学区域的频率下有效的室温运行所必需的。 这些器件已经成功地实现了10微米区域的直接和外差检测。

公开(公告)号：US4310570A

公开(公告)日：1982-01-12

申请号：US145625

申请日：1980-05-01

申请人： Joseph A. Calviello

发明人： Joseph A. Calviello

IPC分类号： H01L21/24 ,  H01L21/285 ,  H01L21/338 ,  H01L29/45 ,  H01L29/78 ,  H01L29/80 ,  H01L29/812 ,  H01L21/283

CPC分类号： H01L29/66856 ,  H01L21/242 ,  H01L21/28575 ,  H01L29/452 ,  H01L29/7839 ,  H01L29/806 ,  H01L29/812 ,  Y10S148/084

摘要： A method for forming ohmic contacts of gold and germanium gold on a gallium arsenide substrate in which a layer of silicon dioxide is placed over the gold in the contact area prior to sinter alloying to improve wetting and reduce contact resistance.

摘要翻译： 在砷化镓衬底上形成金和锗金的欧姆接触的方法，其中在烧结合金化之前，将二氧化硅层置于接触区域中的金上，以改善润湿性并降低接触电阻。