公开(公告)号：US07307454B1

公开(公告)日：2007-12-11

申请号：US11130017

申请日：2005-05-16

申请人： Joseph D. Wert

发明人： Joseph D. Wert

IPC分类号： H03K10/0185

CPC分类号： H03K3/356113 ,  H03K17/223

摘要： A level shifter for use in a dual power supply circuit operating from a VDD power supply and a VDDH power supply greater than the VDD power supply. The level shifter indicates to a status circuit in the VDDH power supply domain that the VDD power supply is enabled. The level shifter detects when the VDD power supply is on and sets an enable signal to the status circuit. The level shifter also detects when the VDD power supply is off and clears the enable signal to the status circuit.

摘要翻译： 一个电平转换器，用于从VDD电源工作的双电源电路和大于VDD电源的VDDH电源。 电平移位器向VDDH电源域中的状态电路指示VDD电源已使能。 电平移位器检测VDD电源何时接通，并将状态电路设置为使能信号。 电平转换器还检测VDD电源何时关闭，并将使能信号清除到状态电路。

公开(公告)号：US06683485B1

公开(公告)日：2004-01-27

申请号：US10004747

申请日：2001-12-04

申请人： Joseph D. Wert

发明人： Joseph D. Wert

IPC分类号： H03L500

CPC分类号： H03K19/018528

摘要： A double translation voltage level shifter is provided that includes a first translator comprising thin-gate devices and a second translator comprising thick-gate devices. The first translator is operable to receive an internal power supply voltage associated with an internal voltage domain, to receive a transitional power supply voltage associated with a transitional voltage domain, and to receive internal data. The internal data comprises data in the internal voltage domain. The first translator is also operable to generate transitional data based on the internal data, the internal power supply voltage, and the transitional power supply voltage. The transitional data comprises data in the transitional voltage domain. The second translator is operable to receive an external power supply voltage associated with an external voltage domain. The second translator is also operable to generate external data based on the transitional data and the external power supply voltage. The external data comprises data in the external voltage domain.

摘要翻译： 提供了双平移电压电平移位器，其包括包括薄栅极器件的第一转换器和包括厚栅极器件的第二转换器。 第一翻译器可操作以接收与内部电压域相关联的内部电源电压，以接收与过渡电压域相关联的过渡电源电压并接收内部数据。 内部数据包括内部电压域中的数据。 第一个翻译器还可以根据内部数据，内部电源电压和过渡电源电压产生过渡数据。 过渡数据包括过渡电压域中的数据。 第二转换器可操作以接收与外部电压域相关联的外部电源电压。 第二翻译器还可操作以基于过渡数据和外部电源电压产生外部数据。 外部数据包括外部电压域中的数据。

公开(公告)号：US06437958B1

公开(公告)日：2002-08-20

申请号：US09489540

申请日：2000-01-21

申请人： Richard L. Duncan ,  Joseph D. Wert

发明人： Richard L. Duncan ,  Joseph D. Wert

IPC分类号： H02H900

CPC分类号： H03K19/00315

摘要： An output driver prevents gate oxide breakdown and reverse charge leakage from a bus to the internal power supply. When the voltage on the bus exceeds the internal supply voltage or when the driver is powered down, a reference voltage generator provides intermediate voltages to prevent the development of excessive gate-source, gate-drain, and gate-backgate voltages in the driver. An upper protection circuit and a lower protection circuit multiplex the intermediate voltages to ensure driver protection and proper operation. A buffering circuit turns off a buffering transistor to block charge leakage to the internal power supply when the bus voltage is greater than the internal power supply voltage. A logic protection circuit prevents the bus voltage from appearing at the control terminal of the driver.

摘要翻译： 输出驱动器防止栅极氧化物故障和从总线向内部电源的反向电荷泄漏。 当总线上的电压超过内部电源电压或驱动器断电时，参考电压发生器提供中间电压，以防止驱动器中过多的栅极 - 源极，栅极 - 漏极和栅极 - 背栅极电压的发展。 上保护电路和下保护电路复用中间电压，以确保驱动器保护和正常工作。 当总线电压大于内部电源电压时，缓冲电路关闭缓冲晶体管以阻止对内部电源的电荷泄漏。 逻辑保护电路可防止总线电压出现在驱动器的控制端。

公开(公告)号：US07642600B1

公开(公告)日：2010-01-05

申请号：US11635321

申请日：2006-12-07

申请人： Joseph D. Wert

发明人： Joseph D. Wert

IPC分类号： H01L23/62

CPC分类号： H03K19/00315 ,  H01L27/0251

摘要： A system and method are disclosed for providing an integrated circuit low voltage thin gate input/output structure with thick gate overvoltage/backdrive protection. In an advantageous embodiment of the present invention, a transfer gate of the input/output structure comprises at least one thick gate native (or depletion) n-channel metal oxide semiconductor (NMOS) transistor that is connected to an output pad node of the input/output structure. The thick gate native (or depletion) NMOS transistor prevents current from the output pad node from entering the input/output structure when a voltage level of the output pad node is high.

摘要翻译： 公开了一种用于提供具有厚栅极过压/反向驱动保护的集成电路低电压薄栅极输入/输出结构的系统和方法。 在本发明的有利实施例中，输入/输出结构的传输门包括至少一个厚栅天生（或耗尽）n沟道金属氧化物半导体（NMOS）晶体管，其连接到输入的输出焊盘节点 /输出结构。 当输出焊盘节点的电压电平高时，厚栅极本征（或耗尽）NMOS晶体管防止来自输出焊盘节点的电流进入输入/输出结构。

公开(公告)号：US06960940B1

公开(公告)日：2005-11-01

申请号：US10837812

申请日：2004-05-03

申请人： Joseph D. Wert ,  Angela H. Wang

发明人： Joseph D. Wert ,  Angela H. Wang

IPC分类号： G01R31/28 ,  G06F1/24 ,  H03K5/1534 ,  H03K5/19 ,  H03K9/06

CPC分类号： H03K5/1534 ,  G01R31/2853 ,  G06F1/24 ,  H03K5/19

摘要： A latch for detecting a state transition of an input signal and generating a self-clearing reset signal on an output. The latch comprises: 1) a transfer gate for passing the input signal to a first node when the input transfer gate is enabled; 2) a transition detector for detecting a transition of the first node from a first to a second state, wherein the transition detector, in response to the transition, disables the transfer gate and enables the reset signal; and 3) a feedback loop circuit for detecting enabling of the reset signal. The feedback loop circuit, in response to the enabling, changes the first node from the second state back to the first state. The transition detector, in response to the changing of the first node back to the first state, disables the reset signal.

摘要翻译： 用于检测输入信号的状态转换并在输出上产生自清零复位信号的锁存器。 锁存器包括：1）当输入传输门被使能时，用于将输入信号传递到第一节点的传输门; 2）一种用于检测第一节点从第一状态到第二状态的转变的转换检测器，其中，所述转换检测器响应于所述转换而禁用所述传输门并启用所述复位信号; 以及3）用于检测复位信号的使能的反馈回路电路。 响应于启用，反馈回路电路将第一节点从第二状态改变到第一状态。 转换检测器响应于第一节点改变回到第一状态而禁用复位信号。

公开(公告)号：US5406140A

公开(公告)日：1995-04-11

申请号：US72896

申请日：1993-06-07

申请人： Joseph D. Wert ,  Richard L. Duncan

发明人： Joseph D. Wert ,  Richard L. Duncan

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0948

CPC分类号： H03K19/018521 ,  H03K19/00315 ,  H03K19/01721

摘要： A voltage translator is provided that translates a lower voltage to a higher voltage, for example, a 3.3 V voltage to a 5.0 V voltage. The 3.3 V voltage is received on source/drain terminal N1 of an NMOS transistor. The transistor gate is at 3.3 V. The other source/drain terminal N2 of the transistor is connected to an input of a CMOS inverter powered by 5.0 V. The inverter output is connected to the gate of a PMOS transistor connected between 5.0 V and terminal N2. The PMOS transistor pulls terminal N2 to 5.0 V when terminal N1 is at 3.3 V. The same translator is suitable for translating a 5.0 V voltage on terminal N1 to 3.3 V on terminal N2 if the inverter is powered by 3.3 V and the PMOS transistor is connected between 3.3 V and terminal N2. Also, an output driver is provided in which a voltage protection circuitry prevents charge leakage from the driver output terminal to the driver's power supply when the voltage on the bus connected to the output terminal exceeds the power supply voltage.

摘要翻译： 提供电压转换器，其将较低电压转换为较高电压，例如3.3V电压至5.0V电压。 在NMOS晶体管的源极/漏极端子N1上接收3.3V的电压。 晶体管栅极为3.3V。晶体管的另一个源极/漏极端子N2连接到由5.0V供电的CMOS反相器的输入。反相器输出连接到连接在5.0 V和端子之间的PMOS晶体管的栅极 N2。 当端子N1为3.3V时，PMOS晶体管将端子N2拉至5.0V。如果变频器由3.3V供电，则PMOS晶体管为相同的转换器适用于将N1端子上的5.0 V电压转换为端子N2上的3.3 V 连接在3.3 V和端子N2之间。 此外，提供一种输出驱动器，其中当连接到输出端子的总线上的电压超过电源电压时，电压保护电路防止从驱动器输出端子到驱动器电源的电荷泄漏。

公开(公告)号：US06906553B1

公开(公告)日：2005-06-14

申请号：US10440033

申请日：2003-05-16

申请人： Joseph D. Wert

发明人： Joseph D. Wert

IPC分类号： H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/00315

摘要： A logic gate for use in an electronic system comprising: i) a first component operating from a low voltage power supply rail; ii) a second component operating from a high voltage power supply rail; and iii) an over-voltage protection circuit that detects an over-voltage on an output pad of the first component and, in response to the detection generates from the over-voltage a generated power supply voltage and a generated reference signal. According to an advantageous embodiment of the present invention, the logic gate comprises a plurality of transistors, wherein the plurality of transistors are powered by the generated power supply voltage and at least one of the plurality of transistors is turned ON and OFF by the generated reference signal.

摘要翻译： 一种用于电子系统的逻辑门，包括：i）从低电压电源轨操作的第一组件; ii）从高压电源轨操作的第二部件; 以及iii）过电压保护电路，其检测所述第一部件的输出焊盘上的过电压，并且响应于所述检测，从所述过电压产生产生的电源电压和产生的参考信号。 根据本发明的有利实施例，逻辑门包括多个晶体管，其中多个晶体管由所产生的电源电压供电，并且多个晶体管中的至少一个通过所产生的参考而导通和截止 信号。

公开(公告)号：US06853221B1

公开(公告)日：2005-02-08

申请号：US10037180

申请日：2001-10-23

申请人： Joseph D. Wert

发明人： Joseph D. Wert

IPC分类号： H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223

摘要： A power monitor circuit for notifying processing circuits operating from a first power supply (VDD) that a second power supply (VDDIO) is powered up. VDDIO is greater than VDD. The power monitor circuit comprises: 1) a voltage divider circuit coupled between the second power supply and ground having an output node that goes high when the second power supply is powered up; and 2) an odd number of serially connected inverters operating from the first power supply. An input of a first serially connected inverter is connected to the voltage divider circuit output node. An output of the last serially connected inverter produces a status signal that is the inverse of the voltage divider circuit output node. The status signal is an input to the voltage divider circuit that minimizes the voltage divider circuit—s current consumption when the second power supply is ON, while maintaining the status signal value.

摘要翻译： 一种电力监控电路，用于通知处理电路从第一电源（VDD）工作，使第二电源（VDDIO）上电。 VDDIO大于VDD。 功率监视电路包括：1）耦合在第二电源和地之间的分压器电路，其具有当第二电源供电时变高的输出节点; 和2）从第一电源操作的奇数串联逆变器。 第一串联逆变器的输入端连接到分压器电路输出节点。 最后一个串联逆变器的输出产生与分压器电路输出节点相反的状态信号。 状态信号是分压器电路的输入，当维持第二电源接通时，分压器电路的电流消耗最小化，同时保持状态信号值。

公开(公告)号：US06731139B1

公开(公告)日：2004-05-04

申请号：US10171393

申请日：2002-06-12

申请人： Joseph D. Wert ,  Angela H. Wang

发明人： Joseph D. Wert ,  Angela H. Wang

IPC分类号： H03K906

CPC分类号： H03K5/1534 ,  G01R31/2853 ,  G06F1/24 ,  H03K5/19

摘要： A latch for detecting a state transition of an input signal and generating a self-clearing reset signal on an output. The latch comprises: 1) a transfer gate for passing the input signal to a first node when the input transfer gate is enabled; 2) a transition detector for detecting a transition of the first node from a first to a second state, wherein the transition detector, in response to the transition, disables the transfer gate and enables the reset signal; and 3) a feedback loop circuit for detecting enabling of the reset signal. The feedback loop circuit, in response to the enabling, changes the first node from the second state back to the first state. The transition detector, in response to the changing of the first node back to the first state, disables the reset signal.

摘要翻译： 用于检测输入信号的状态转换并在输出上产生自清零复位信号的锁存器。 锁存器包括：1）当输入传输门被使能时，用于将输入信号传递到第一节点的传输门; 2）一种用于检测第一节点从第一状态到第二状态的转变的转换检测器，其中，所述转换检测器响应于所述转换而禁用所述传输门并启用所述复位信号; 以及3）用于检测复位信号的使能的反馈回路电路。 响应于启用，反馈回路电路将第一节点从第二状态改变到第一状态。 转换检测器响应于第一节点改变回到第一状态而禁用复位信号。

公开(公告)号：US06384631B1

公开(公告)日：2002-05-07

申请号：US09844183

申请日：2001-04-27

申请人： Joseph D. Wert ,  William E. Ballachino

发明人： Joseph D. Wert ,  William E. Ballachino

IPC分类号： H03K190948

CPC分类号： H03K19/018521

摘要： There is disclosed a voltage level shifter that receives an input signal having a maximum Logic 1 value of VDD and produces an output signal having a maximum Logic 1 value of VDDI/O, where VDDI/O is greater than VDD. The voltage level shifter comprises: 1) a first circuit branch comprising A) a first p-type transistor having a source coupled to a first power supply having a level of VDDI/O and B) a first n-type transistor having a source coupled to ground, a drain coupled to a drain of the first p-type transistor, and a gate coupled to the input data signal; and 2) a second circuit branch comprising A) a second p-type transistor having a source coupled to the first power supply and a gate coupled to a drain of the first n-type transistor and B) a second n-type transistor having a source coupled to ground, a drain coupled to i) a drain of the second p-type transistor and ii) a gate of the first p-type transistor, and a gate coupled to an inverted copy of the input data signal, wherein a drain current of the first p-type transistor is larger than a drain current of the second p-type transistor for the same gate-to-source voltage, such that the first p-type transistor turns on faster than the second p-type transistor if the first power supply is powered up to VDDI/O when the first and second n-type transistors are off.

摘要翻译： 公开了一种电压电平转换器，其接收具有VDD的最大逻辑1值的输入信号，并产生具有VDDI / O的最大逻辑1值的输出信号，其中VDDI / O大于VDD。 电压电平移位器包括：1）第一电路支路，包括A）第一p型晶体管，其源极耦合到具有VDDI / O电平的第一电源，以及B）第一n型晶体管，其源极耦合 接地，耦合到第一p型晶体管的漏极的漏极和耦合到输入数据信号的栅极; 以及2）第二电路支路，包括A）具有耦合到所述第一电源的源极和耦合到所述第一n型晶体管的漏极的栅极的第二p型晶体管，以及B）第二n型晶体管，其具有 源极，其耦合到i）第二p型晶体管的漏极，以及ii）第一p型晶体管的栅极和耦合到输入数据信号的反相的栅极，其中漏极 对于相同的栅极至源极电压，第一p型晶体管的电流大于第二p型晶体管的漏极电流，使得第一p型晶体管比第二p型晶体管导通更快，如果 当第一和第二n型晶体管关闭时，第一电源供电到VDDI / O。