利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

241 条记录 (耗时 0.025 秒)

    Systems and methods for memory controller reference voltage calibration
    2.
    发明授权
    Systems and methods for memory controller reference voltage calibration 有权
    内存控制器参考电压校准的系统和方法

    公开(公告)号：US09111603B1

    公开(公告)日：2015-08-18

    申请号：US13409077

    申请日：2012-02-29

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  G11C5/14

    摘要： An integrated circuit may include a memory controller that interfaces with memory via one or more ports. A given port may be coupled to a comparator that receives data signals from the memory and a reference voltage signal and produces a corresponding output signal that identifies whether the data signals are logic one signals or logic zero signals. The memory controller may include detection circuitry coupled to the port that produces a target reference voltage signal for calibration of the reference voltage signal. The memory controller may include circuitry that produces the reference voltage signal based on control signals received from control circuitry. The control circuitry may generate the control signals to calibrate the reference voltage signal based on the target reference voltage.

    摘要翻译： 集成电路可以包括经由一个或多个端口与存储器接口的存储器控​​制器。 给定端口可以耦合到从存储器接收数据信号的比较器和参考电压信号，并产生相应的输出信号，其识别数据信号是逻辑一个信号还是逻辑零信号。 存储器控制器可以包括耦合到端口的检测电路，其产生用于校准参考电压信号的目标参考电压信号。 存储器控制器可以包括基于从控制电路接收的控制信号产生参考电压信号的电路。 控制电路可以产生控制信号，以基于目标参考电压来校准参考电压信号。

    Write-leveling implementation in programmable logic devices
    3.
    发明授权
    Write-leveling implementation in programmable logic devices 有权
    在可编程逻辑器件中编写调平实现

    公开(公告)号：US08671303B2

    公开(公告)日：2014-03-11

    申请号：US13349228

    申请日：2012-01-12

    申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

    发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

    IPC分类号： G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

    摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

    摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

    Variation compensation circuitry for memory interface
    5.
    发明授权
    Variation compensation circuitry for memory interface 有权
    用于存储器接口的变差补偿电路

    公开(公告)号：US08565034B1

    公开(公告)日：2013-10-22

    申请号：US13249954

    申请日：2011-09-30

    申请人： Sean Shau-Tu Lu ,  Joseph Huang ,  Yan Chong ,  Pradeep Nagarajan ,  Chiakang Sung

    发明人： Sean Shau-Tu Lu ,  Joseph Huang ,  Yan Chong ,  Pradeep Nagarajan ,  Chiakang Sung

    IPC分类号： G11C7/00 ,  G11C7/22

    CPC分类号： G11C7/22 ,  G06F13/1689

    摘要： Integrated circuits may include memory interface circuitry operable to communicate with system memory. The memory interface circuitry may receive data and data strobe signals from system memory during read operations. The memory interface circuitry may include de-skew circuitry and dynamic variation compensation circuitry. The de-skew circuitry may be configured during calibration procedures to reduce skew between the data and data strobe signals. The dynamic variation compensation circuitry may be used in real time to compensate for variations in operating conditions. The dynamic variation compensation circuitry may include a phase generation circuit operable to generate data strobe signals having different phases, an edge detection circuit operable to detect leading/trailing edge failures, a control circuit operable to control a counter, and an adjustable delay circuit that is controlled by the counter and that is operable to properly position the data signal with respect to its corresponding data strobe signal.

    摘要翻译： 集成电路可以包括可操作以与系统存储器通信的存储器接口电路。 存储器接口电路可以在读取操作期间从系统存储器接收数据和数据选通信号。 存储器接口电路可以包括去偏移电路和动态变化补偿电路。 可以在校准过程期间配置去偏移电路，以减少数据和数据选通信号之间的偏差。 可以实时地使用动态变化补偿电路来补偿操作条件的变化。 动态变化补偿电路可以包括可产生具有不同相位的数据选通信号的相位产生电路，可操作以检测前沿/后沿故障的边缘检测电路，可操作以控制计数器的控制电路和可调延迟电路， 由计数器控制，并且可操作以相对于其对应的数据选通信号适当地定位数据信号。

    USB MEMORY STICK WITH A HINGED SAFETY HOOK
    6.
    发明申请
    USB MEMORY STICK WITH A HINGED SAFETY HOOK 有权
    USB记忆棒带有铰链安全钩

    公开(公告)号：US20130265709A1

    公开(公告)日：2013-10-10

    申请号：US13441067

    申请日：2012-04-06

    申请人： Joseph HUANG

    发明人： Joseph HUANG

    IPC分类号： G06F1/16

    CPC分类号： H05K5/0278 ,  G06F21/88

    摘要： A USB memory stick includes comprises a casing comprising opposing top and bottom sides and a bottom opening in said bottom side, a PC board comprising a USB interface circuit and a memory chip package, a tray holding the PC board in the casing, a safety hook for fastening to a belt or strip-like object, and a hinge coupled between the casing and the safety hook for allowing a limited angle of rotation between the casing and the safety hook.

    摘要翻译： USB记忆棒包括：壳体，包括相对的顶侧和底侧;以及位于所述底侧的底部开口; PC板，包括USB接口电路和存储芯片封装;将所述PC板保持在所述壳体中的托盘，安全钩 用于紧固到带或条状物体，以及联接在壳体和安全钩之间的铰链，用于允许壳体和安全钩之间的有限的旋转角度。

    Programmable high-speed interface
    7.
    发明授权
    Programmable high-speed interface 有权

    公开(公告)号：US08487665B2

    公开(公告)日：2013-07-16

    申请号：US13149168

    申请日：2011-05-31

    申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

    发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

    IPC分类号： H03B1/00

    CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

    摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

    High-performance memory interface circuit architecture
    8.
    发明授权
    High-performance memory interface circuit architecture 有权
    高性能存储器接口电路架构

    公开(公告)号：US08305121B1

    公开(公告)日：2012-11-06

    申请号：US13168499

    申请日：2011-06-24

    申请人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    发明人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0805

    摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

    摘要翻译： 可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。 然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略 相移控制设置，以产生精细的相移控制设置。 粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

    WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
    9.
    发明申请
    WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES 有权
    可编程逻辑器件中的写层次实现

    公开(公告)号：US20120106264A1

    公开(公告)日：2012-05-03

    申请号：US13349228

    申请日：2012-01-12

    申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

    发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

    IPC分类号： G11C7/10 ,  H03L7/00 ,  G11C7/22

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

    摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

    摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

    Write-leveling implementation in programmable logic devices
    10.
    发明授权
    Write-leveling implementation in programmable logic devices 有权
    在可编程逻辑器件中编写调平实现

    公开(公告)号：US08122275B2

    公开(公告)日：2012-02-21

    申请号：US11843123

    申请日：2007-08-22

    申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

    发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

    IPC分类号： G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

    摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

    摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。