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公开(公告)号：US07315595B2
公开(公告)日：2008-01-01
申请号：US10743614
申请日：2003-12-22
IPC分类号： H04L7/00
CPC分类号： H04L7/0079 , H03L7/0802 , H03L7/085 , H03L7/091 , H04B1/7085 , H04L7/0331
摘要： Methods, and arrangements for extension of clock and data recovery (CDR) loop latency and deactivation of CDR circuits are disclosed. In particular, embodiments address situations in which a receiver, designed to handle spread spectrum clocking, may not always or continuously encounter spread spectrum signals. As a result, power consumption by the receivers may be reduced. Embodiments identify situations in which spread spectrum clocking is unnecessary and may adapt the CDR loop to operate with less power consumption by, e.g., reducing the operating frequency of CDR circuits. For instance, some embodiments employ a flywheel circuit, incorporated into many spread spectrum CDR loops to accelerate adjustments to a sampling clock, to determine when spread spectrum signals are not being encountered. A loop latency controller may then, advantageously, reduce power consumption by reducing frequencies of operation and voltages, and merging or simplifying stages.
摘要翻译： 公开了用于延长时钟和数据恢复（CDR）环路延迟和CDR电路的去激活的方法和装置。 特别地，实施例解决了设计用于处理扩频时钟的接收机可能不总是或连续地遇到扩频信号的情况。 结果，可以减少接收机的功率消耗。 实施例识别出不需要扩频时钟的情况，并且可以通过例如降低CDR电路的工作频率来适应CDR环路以更少的功率消耗来操作。 例如，一些实施例采用飞轮电路，并入许多扩频CDR环路中以加速对采样时钟的调整，以确定何时不会遇到扩频信号。 然后，有利地，循环等待时间控制器通过减少操作频率和电压，以及合并或简化阶段来降低功耗。
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2.发明授权Method and apparatus for generating non-skewed complementary signals through interpolation 失效通过插值产生非偏斜互补信号的方法和装置公开(公告)号：US07084689B2
公开(公告)日：2006-08-01
申请号：US10988455
申请日：2004-11-12
IPC分类号： H03K3/00
CPC分类号： G06F1/04 , H03K5/1515
摘要： A complementary digital signal generator circuit and method receives a periodic digital signal, such as a square wave, as an input and generates at the output complementary versions of the digital signal delayed by matching increments of delay with minimum skew at GHz frequencies. The digital signal is processed by inverters and interpolators which may be readily matched in size and functional characteristics by close proximity placement on integrated circuits. An inverted and first delayed version of the original digital signal is applied to both inputs of a first interpolator, to generate at the output of the interpolator the complement of the digital signal as delayed by the first delayed and the delay introduced by the interpolator. The inverted and first delayed digital signal is inverted and second delayed by a second matching inverter and applied as one input to a second interpolator. The second input of the second interpolator is the original digital signal. The output of the second interpolator is the digital signal delayed by a corresponding combination of the first delay and the delay introduced by the second interpolator. When the first and second interpolators are matched, in the manner of the first and second inverters, the two interpolator outputs provide the digital signal and its complement with substantially no skew and matching increments of delay.
摘要翻译： 互补的数字信号发生器电路和方法接收诸如方波的周期性数字信号作为输入，并在数字信号的输出互补版本处产生延迟的具有GHz频率的最小偏移的延迟匹配延迟的输出互补版本。 数字信号由逆变器和内插器处理，其可以通过集成电路上的紧密贴近来容易地匹配尺寸和功能特性。 将原始数字信号的反相和第一延迟版本应用于第一内插器的两个输入，以在内插器的输出处产生由第一延迟延迟的延迟和由内插器引入的延迟的数字信号的补码。 反相和第一延迟数字信号被反相，并且被第二匹配反相器延迟，并作为一个输入施加到第二内插器。 第二内插器的第二输入是原始数字信号。 第二内插器的输出是由第二内插器引入的第一延迟和延迟的相应组合延迟的数字信号。 当第一和第二内插器被匹配时，以第一和第二反相器的方式，两个内插器输出提供数字信号及其补码，基本上没有偏移和匹配的延迟增量。
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公开(公告)号：US20050138492A1
公开(公告)日：2005-06-23
申请号：US10698138
申请日：2003-10-30
IPC分类号： G06F11/00
摘要： A system for designing a communication link for use in a data processing system, includes a parameter generator and an internal link model. The parameter generator allows a user to specify a first set of link parameters. The generator derives a set of internal parameters from the first set of parameters. The internal link model, which includes a set of configurable link cells, receives the internal parameters and instantiates each link cell based on the internal parameters. The system further includes a channel simulator or similar means for modeling a bit error rate (BER) of the instantiated communication link and may further include an estimator of the link's area and power consumption. In an embodiment that protects the intellectual property associated with the internal model from the system user, the parameter generator prevents the user from directly accessing the internal parameters and the generic link model.
摘要翻译： 一种用于设计用于数据处理系统的通信链路的系统，包括参数发生器和内部链路模型。 参数生成器允许用户指定第一组链接参数。 生成器从第一组参数中导出一组内部参数。 包括一组可配置链路单元的内部链路模型接收内部参数，并根据内部参数实例化每个链路单元。 该系统还包括信道模拟器或用于对实例通信链路的误码率（BER）进行建模的类似装置，并且还可以包括链路区域和功耗的估计器。 在保护与内部模型相关联的知识产权与系统用户的实施例中，参数生成器阻止用户直接访问内部参数和通用链接模型。
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公开(公告)号：US20050136867A1
公开(公告)日：2005-06-23
申请号：US10743653
申请日：2003-12-22
摘要： Methods, and arrangements for power reduction in links, such as transmitters and receivers, based upon global decisions such as the data transmission frequencies, communications media, and traffic types associated with links, are disclosed. In particular, embodiments take advantage of high-level decisions by reconfiguring internal circuits of transmitters and receivers of links to reduce power consumption. At the global level, a decision determines the links that are active, the data frequency at which the links operate, and the media through which the links transmit the data. At the local level, the links receive the decisions and reconfigure circuitry automatically to minimize power based upon the decisions. In some embodiments, the links may receive the decisions in the form of power modes. In further embodiments, the links may receive settings such as on/off settings, data frequency settings, and traffic/media settings, the combination of which indicates power modes.
摘要翻译： 公开了基于诸如数据传输频率，通信媒体和与链路相关联的业务类型等全球决策的链路中诸如发射机和接收机之间的功率降低的方法和装置。 特别地，实施例通过重新配置链路的发射机和接收机的内部电路来降低功耗，来利用高级决策。 在全球层面，一个决定决定了活跃的链接，链接操作的数据频率以及链接传输数据的媒体。 在地方层面，链路会自动接收决定并自动重新配置电路，以便根据决策最小化功率。 在一些实施例中，链路可以以功率模式的形式接收决定。 在另外的实施例中，链路可以接收诸如开/关设置，数据频率设置和业务/媒体设置的设置，其组合指示功率模式。
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公开(公告)号：US06621358B2
公开(公告)日：2003-09-16
申请号：US10015384
申请日：2001-12-17
IPC分类号： H03B500
CPC分类号： H03K5/133 , H03K3/0322 , H03K2005/00208 , H03K2005/00234
摘要： In a first form, a voltage controlled oscillator includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. The control elements are operable to receive respective differential inputs and to generate non-inverted outputs with variable delays. The control element delays are variable responsive to respective differential control voltages.
摘要翻译： 在第一形式中，压控振荡器包括以环形连接的延迟单元，以及连接到选择性地旁路各组延迟单元的控制元件。 延迟单元可操作以接收相应的差分输入并产生反相输出。 控制元件可操作以接收相应的差分输入并产生具有可变延迟的非反相输出。 响应于各个差分控制电压，控制元件延迟是可变的。
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6.发明申请公开(公告)号：US20080232530A1
公开(公告)日：2008-09-25
申请号：US12136205
申请日：2008-06-10
申请人： Juan Antonio Carballo , Hayden Clavie Cranford , Gareth John Nicholls , Vernon Roberts Norman , Brian Joel Schuh
发明人： Juan Antonio Carballo , Hayden Clavie Cranford , Gareth John Nicholls , Vernon Roberts Norman , Brian Joel Schuh
IPC分类号： H04L7/00
CPC分类号： H04B17/382 , H04B17/24 , H04B17/345
摘要： A method, circuit and system for altering the power consumption in communication links. A type of noise and an amount of jitter in a signal transmitted across a communication link is measured. Upon determining the contribution of the measured noise to the measured jitter in the signal, the measured noise is classified based on such contribution and the intensity of the measured jitter. The power consumption in a component(s) of the communication link may be adjusted based on the classification of the measured noise. For example, if the measured noise is classified as being a low amount of noise, then the power consumption of the component(s) may be reduced such as by lowering the voltage of the power supply and/or reducing the complexity of the circuitry. By reducing the power consumption when the communication link is not subject to the worst-case condition, a savings in power consumption may be made.
摘要翻译： 一种用于改变通信链路功耗的方法，电路和系统。 测量通过通信链路传输的信号中的噪声类型和抖动量。 在确定测量的噪声对信号中测得的抖动的贡献时，测量的噪声基于这样的贡献和所测量的抖动的强度进行分类。 可以基于测量的噪声的分类来调整通信链路的组件中的功率消耗。 例如，如果测量的噪声被分类为低的噪声量，则可以减少部件的功率消耗，例如通过降低电源的电压和/或降低电路的复杂性。 当通信链路不受最坏情况的影响时，通过降低功耗，可以节省功耗。
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公开(公告)号：US07353154B2
公开(公告)日：2008-04-01
申请号：US10698138
申请日：2003-10-30
IPC分类号： G06F17/60
摘要： A system for designing a communication link for use in a data processing system, includes a parameter generator and an internal link model. The parameter generator allows a user to specify a first set of link parameters. The generator derives a set of internal parameters from the first set of parameters. The internal link model, which includes a set of configurable link cells, receives the internal parameters and instantiates each link cell based on the internal parameters. The system further includes a channel simulator or similar means for modeling a bit error rate (BER) of the instantiated communication link and may further include an estimator of the link's area and power consumption. In an embodiment that protects the intellectual property associated with the internal model from the system user, the parameter generator prevents the user from directly accessing the internal parameters and the generic link model.
摘要翻译： 一种用于设计用于数据处理系统的通信链路的系统，包括参数发生器和内部链路模型。 参数生成器允许用户指定第一组链接参数。 生成器从第一组参数中导出一组内部参数。 包括一组可配置链路单元的内部链路模型接收内部参数，并根据内部参数实例化每个链路单元。 该系统还包括信道模拟器或用于对实例化的通信链路的误码率（BER）进行建模的类似装置，并且还可以包括链路的面积和功率消耗的估计器。 在保护与内部模型相关联的知识产权与系统用户的实施例中，参数生成器阻止用户直接访问内部参数和通用链接模型。
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公开(公告)号：US07269397B2
公开(公告)日：2007-09-11
申请号：US11424209
申请日：2006-06-14
申请人： Juan-Antonio Carballo , Jeffrey L. Burns , Ivan Vo
发明人： Juan-Antonio Carballo , Jeffrey L. Burns , Ivan Vo
IPC分类号： H04B17/02
CPC分类号： H04B17/20
摘要： A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.
摘要翻译： 用于测量通信链路质量的方法和装置提供对实现通信链路的特定误码率（BER）的难度的精确的片上估计。 连接到来自时钟/数据恢复（CDR）电路的内部信号的低成本/复杂度的累加器电路提供接收信号中的高频和低频抖动的量度。 低频抖动测量用于校正可能包含错误的高频抖动测量。 校正的输出可用于调整链路的操作特性或以其他方式评估链路的操作裕度。 可以通过从测量的高频抖动中减去一部分低频抖动测量来执行校正，或者可以使用低频抖动测量的值来选择两个或更多个校正因子，然后将其应用于高频抖动 抖动测量。
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公开(公告)号：US20060171477A1
公开(公告)日：2006-08-03
申请号：US11050605
申请日：2005-02-03
申请人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H04L25/00
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver stages and portions are selectively disabled when the transmission circuit is in a lower-power operating mode. A single-ended to differential converter circuit can be used to construct a differential signal for output to the final driver stage. The selection of power mode can be made via feedback from a channel quality measurement unit or may be hardwired or selected under programmatic control. The longer delay or skew of the lower-power single-ended mode is compensated for by the relaxed requirements of the channel when conditions permit the use of the lower-power single-ended mode.
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10.发明申请公开(公告)号：US20060103445A1
公开(公告)日：2006-05-18
申请号：US10988455
申请日：2004-11-12
申请人： Juan-antonio Carballo , Fadi Gebara
发明人： Juan-antonio Carballo , Fadi Gebara
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , H03K5/1515
摘要： A complementary digital signal generator circuit and method receives a periodic digital signal, such as a square wave, as an input and generates at the output complementary versions of the digital signal delayed by matching increments of delay with minimum skew at GHz frequencies. The digital signal is processed by inverters and interpolators which may be readily matched in size and functional characteristics by close proximity placement on integrated circuits. An inverted and first delayed version of the original digital signal is applied to both inputs of a first interpolator, to generate at the output of the interpolator the complement of the digital signal as delayed by the first delayed and the delay introduced by the interpolator. The inverted and first delayed digital signal is inverted and second delayed by a second matching inverter and applied as one input to a second interpolator. The second input of the second interpolator is the original digital signal. The output of the second interpolator is the digital signal delayed by a corresponding combination of the first delay and the delay introduced by the second interpolator. When the first and second interpolators are matched, in the manner of the first and second inverters, the two interpolator outputs provide the digital signal and its complement with substantially no skew and matching increments of delay.
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