公开(公告)号：US07861196B2

公开(公告)日：2010-12-28

申请号：US12023512

申请日：2008-01-31

申请人： Judy Huckabay ,  Weiping Fang ,  Chung-Shin Kang ,  Shiying Zhou

发明人： Judy Huckabay ,  Weiping Fang ,  Chung-Shin Kang ,  Shiying Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.

摘要翻译： 一些实施例提供了用于识别不符合制造约束的设计布局内的图案的误差标记的方法和系统。 一些实施例将区域从错误标记区域扩展以提取用于分解分析的模式。 一些实施例将提取的图案与存储在库中的已知图案进行比较，库中还存储了每个已知图案的至少一个先前计算的分解解。 对于库中存在的提取模式，一些实施例从库中检索先前计算的分解解。 对于在库内不存在的提取模式，一些实施例使用一个或多个模拟来确定所提取模式的分解解。 所得到的分解解代替了设计布局中提取的图案，从而产生了原始布局的变体，该变体包含该模式的分解解。

公开(公告)号：US08656321B1

公开(公告)日：2014-02-18

申请号：US13183749

申请日：2011-07-15

申请人： Judy Huckabay ,  Milind Weling ,  Abdurrahman Sezginer

发明人： Judy Huckabay ,  Milind Weling ,  Abdurrahman Sezginer

IPC分类号： G06F17/50

CPC分类号： H01L21/0338 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/30621

摘要： Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between two adjacent sets. In such embodiment, the sets of parallel line features along with the connection features are formed using two lithographic masks, without a need for an additional mask layer to form the connection features. In other embodiments, other features in addition to the connection features can be added in the same mask layer.

摘要翻译： 公开了使用双重图案化的半导体器件制造技术的方法。 根据本发明的各种实施例，提供了使用自对准双重图案化的半导体器件制造方法。 本发明的特定实施例允许使用两个光刻操作创建逻辑电路图案。 本发明的一个实施例采用自对准双重图案化来定义具有两个相邻组之间的连接特征的两组或多组平行线特征。 在这种实施例中，使用两个光刻掩模来形成平行线特征的集合以及连接特征，而不需要额外的掩模层来形成连接特征。 在其他实施例中，除了连接特征之外的其他特征可以添加在相同的掩模层中。

公开(公告)号：US08209656B1

公开(公告)日：2012-06-26

申请号：US12251455

申请日：2008-10-14

申请人： Xiaojun Wang ,  Yuane Qiu ,  Prasanti Uppaluri ,  Judy Huckabay ,  Tianhao Zhang

发明人： Xiaojun Wang ,  Yuane Qiu ,  Prasanti Uppaluri ,  Judy Huckabay ,  Tianhao Zhang

IPC分类号： G06F17/50 ,  G06F15/04

CPC分类号： G03F1/70

摘要： Some embodiments provide a method for decomposing a region of an integrated circuit (“IC”) design layout into multiple mask layouts. The method identifies a number of sets of geometries in the design layout region that must be collectively assigned to the multiple mask layouts. The method assigns the geometries in a first group of collectively-assigned sets to different mask layouts without splitting any of the geometries. The method assigns the geometries in a second group of the collectively-assigned sets to different mask layouts in such a way so as to minimize the number of splits in the geometries of the second group.

摘要翻译： 一些实施例提供了一种用于将集成电路（“IC”）设计布局的区域分解为多个掩模布局的方法。 该方法识别设计布局区域中必须集中分配给多个掩码布局的几组几何。 该方法将第一组共同分配的集合中的几何分配给不同的掩码布局，而不分裂任何几何。 该方法以这样的方式将集合分配的集合的第二组中的几何分配给不同的掩模布局，以便最小化第二组的几何形状中的分割数。

公开(公告)号：US07856613B1

公开(公告)日：2010-12-21

申请号：US12264853

申请日：2008-11-04

申请人： Milind Weling ,  Judy Huckabay ,  Abdurrahman Sezginer

发明人： Milind Weling ,  Judy Huckabay ,  Abdurrahman Sezginer

IPC分类号： G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

CPC分类号： H01L21/033 ,  G03F1/00

摘要： Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.

摘要翻译： 本发明的各种实施例提供用于半导体器件制造和生成用于图案化线特征和大特征的目标布局的光掩模的系统和方法。 本发明的实施例涉及使用自对准双重图案来定义线特征和大特征的目标布局的系统和方法。

公开(公告)号：US08679981B1

公开(公告)日：2014-03-25

申请号：US12943808

申请日：2010-11-10

申请人： Milind Weling ,  Judy Huckabay ,  Abdurrahman Sezginer

发明人： Milind Weling ,  Judy Huckabay ,  Abdurrahman Sezginer

IPC分类号： H01L21/302

CPC分类号： H01L21/033 ,  G03F1/00

摘要： Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.

摘要翻译： 本发明的各种实施例提供用于半导体器件制造和生成用于图案化线特征和大特征的目标布局的光掩模的系统和方法。 本发明的实施例涉及使用自对准双重图案来定义线特征和大特征的目标布局的系统和方法。

公开(公告)号：US07310797B2

公开(公告)日：2007-12-18

申请号：US11405029

申请日：2006-04-14

申请人： Judy Huckabay

发明人： Judy Huckabay

IPC分类号： G06F17/50

CPC分类号： G03F7/70466 ,  G03F1/70 ,  G03F7/705

摘要： System and method is disclosed for breaking an integrated circuit design to be printed into two or more exposures by lithographic equipment, each of the two or more exposures has at least the minimum pitch. Together, these multiple exposures print an integrated circuit design that could not be printed in one exposure alone.

摘要翻译： 公开了用于将通过光刻设备打印成两个或多个曝光的集成电路设计的系统和方法，两个或多个曝光中的每一个至少具有最小间距。 一起，这些多重曝光打印出一个集成电路设计，无法单独打印一次曝光。

公开(公告)号：US20070031738A1

公开(公告)日：2007-02-08

申请号：US11405029

申请日：2006-04-14

申请人： Judy Huckabay

发明人： Judy Huckabay

IPC分类号： G03F1/00 ,  G03B27/42 ,  G03C5/00 ,  G03F9/00

CPC分类号： G03F7/70466 ,  G03F1/70 ,  G03F7/705

摘要： System and method is disclosed for breaking a design to be printed into two or more exposures, each of which has at least the minimum pitch. Together, these multiple exposures print a design that could not be printed in one exposure alone.

摘要翻译： 公开了用于将要打印的设计打破为两个或更多个曝光的系统和方法，每个曝光具有至少最小间距。 一起，这些多重曝光打印出一个无法单独打印的设计。

公开(公告)号：US20060265677A1

公开(公告)日：2006-11-23

申请号：US11437794

申请日：2006-05-19

申请人： Louis Scheffer ,  Wolfgang Staud ,  Judy Huckabay

发明人： Louis Scheffer ,  Wolfgang Staud ,  Judy Huckabay

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： An improved method, system, and computer program product is disclosed for increased accuracy for extraction of electrical parameters of an IC design. Extraction is performed upon the expected geometric model of the printed layout once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for performing extraction since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The extracted electrical parameters are checked for acceptability. If not acceptable, then the IC design can be modified to address any identified problems or desired improvements to the design.

摘要翻译： 公开了一种改进的方法，系统和计算机程序产品，用于提高IC设计的电参数的精度。 一旦制造和平版印刷过程效果被考虑，就按照打印布局的预期几何模型进行提取。 这提供了一种更精确的执行提取方法，因为它是被分析的实际预期几何形状，而不是不能准确对应于实际制造的IC产品的理想化模型。 检查提取的电气参数是否可接受。 如果不能接受，则可以修改IC设计以解决任何已识别的问题或对设计的期望改进。

公开(公告)号：US08716135B1

公开(公告)日：2014-05-06

申请号：US12264139

申请日：2008-11-03

申请人： Judy Huckabay ,  Milind Weling ,  Abdurrahman Sezginer

发明人： Judy Huckabay ,  Milind Weling ,  Abdurrahman Sezginer

IPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/306

CPC分类号： H01L21/0338 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/30621

摘要： Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between the sets. In such embodiments, the sets of parallel line features along with the connection features are formed using two lithographic masks, without the need for an additional mask layer to form the connection. In other embodiments, other features in addition to the connection can be added in the same mask layer.

摘要翻译： 公开了使用双重图案化的半导体器件制造技术的方法。 根据本发明的各种实施例，提供了使用自对准双重图案化的半导体器件制造方法。 本发明的特定实施例允许使用两个光刻操作创建逻辑电路图案。 本发明的一个实施例采用自对准双重图案化来定义两组或更多组具有组之间的连接特征的平行线特征。 在这样的实施例中，使用两个光刻掩模来形成平行线特征的集合以及连接特征，而不需要额外的掩模层来形成连接。 在其他实施例中，除了连接之外的其他特征可以添加在相同的掩模层中。

公开(公告)号：US08151219B2

公开(公告)日：2012-04-03

申请号：US12955895

申请日：2010-11-29

申请人： Judy Huckabay ,  Weiping Fang ,  Chung-Shin Kang ,  Shiying Zhou

发明人： Judy Huckabay ,  Weiping Fang ,  Chung-Shin Kang ,  Shiying Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.

摘要翻译： 一些实施例提供了用于识别不符合制造约束的设计布局内的图案的误差标记的方法和系统。 一些实施例将区域从错误标记区域扩展以提取用于分解分析的模式。 一些实施例将提取的图案与存储在库中的已知图案进行比较，库中还存储了每个已知图案的至少一个先前计算的分解解。 对于库中存在的提取模式，一些实施例从库中检索先前计算的分解解。 对于在库内不存在的提取模式，一些实施例使用一个或多个模拟来确定所提取模式的分解解。 所得到的分解解代替了设计布局中提取的图案，从而产生了原始布局的变体，该变体包含该模式的分解解。