公开(公告)号：US07453136B2

公开(公告)日：2008-11-18

申请号：US11588530

申请日：2006-10-27

申请人： Juha Mikko Hakkarainen ,  Juha Seppo Nurminen

发明人： Juha Mikko Hakkarainen ,  Juha Seppo Nurminen

IPC分类号： H01L23/00

CPC分类号： H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor array in an integrated circuit with active unit capacitor cells arranged amongst the dummy unit capacitor cells to provide visual and electrical symmetry. The electrical symmetry provides electrical matching between active unit capacitor cells and the visual symmetry provide process uniformity between the unit capacitor cells. Visual symmetry may be provided by uniform capacitor plate selection and uniform spacing between each. Electrical symmetry is provided by appropriately arranging active unit capacitors amongst dummy unit capacitors in the capacitor array. The capacitor array may be used in an integrated circuit such as for a equally weighted or binary weighted capacitor array or ladder in an analog to digital converter or a digital to analog converter. Methods and rules of layout for arranging the unit capacitors may be manually performed or automatically performed by computer aided design software.

摘要翻译： 集成电路中的电容器阵列，其中有功单元电容器单元布置在虚拟单元电容器单元之间以提供视觉和电对称性。 电对称性提供有源单元电容器单元之间的电气匹配，并且视觉对称性提供单元电容器单元之间的工艺均匀性。 可以通过均匀的电容器板选择和每个之间的均匀间隔来提供视觉对称性。 通过在电容器阵列中的虚拟单元电容器之间适当布置有源单位电容器来提供电对称性。 电容器阵列可以用于集成电路，例如用于模数转换器或数模转换器中的等重或二进制加权电容器阵列或梯形图。 用于布置单元电容器的布局方法和规则可以由计算机辅助设计软件手动执行或自动执行。

公开(公告)号：US07161516B2

公开(公告)日：2007-01-09

申请号：US10624794

申请日：2003-07-22

申请人： Juha Mikko Hakkarainen ,  Juha Seppo Nurminen

发明人： Juha Mikko Hakkarainen ,  Juha Seppo Nurminen

IPC分类号： H03M1/66

CPC分类号： H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor array in an integrated circuit with active unit capacitor cells arranged amongst the dummy unit capacitor cells to provide visual and electrical symmetry. The electrical symmetry provides electrical matching between active unit capacitor cells and the visual symmetry provide process uniformity between the unit capacitor cells. Visual symmetry may be provided by uniform capacitor plate selection and uniform spacing between each. Electrical symmetry is provided by appropriately arranging active unit capacitors amongst dummy unit capacitors in the capacitor array. The capacitor array may be used in an integrated circuit such as for a equally weighted or binary weighted capacitor array or ladder in an analog to digital converter or a digital to analog converter. Methods and rules of layout for arranging the unit capacitors may be manually performed or automatically performed by computer aided design software.

摘要翻译： 集成电路中的电容器阵列，其中有功单元电容器单元布置在虚拟单元电容器单元之间以提供视觉和电对称性。 电对称性提供有源单元电容器单元之间的电气匹配，并且视觉对称性提供单元电容器单元之间的工艺均匀性。 可以通过均匀的电容器板选择和每个之间的均匀间隔来提供视觉对称性。 通过在电容器阵列中的虚拟单元电容器之间适当布置有源单位电容器来提供电对称性。 电容器阵列可以用于集成电路，例如用于模数转换器或数模转换器中的等重或二进制加权电容器阵列或梯形图。 用于布置单元电容器的布局方法和规则可以由计算机辅助设计软件手动执行或自动执行。

公开(公告)号：US5754131A

公开(公告)日：1998-05-19

申请号：US673543

申请日：1996-07-01

申请人： David Byrd Ribner ,  Juha Mikko Hakkarainen ,  David Henry Kenneth Hoe

发明人： David Byrd Ribner ,  Juha Mikko Hakkarainen ,  David Henry Kenneth Hoe

IPC分类号： H03M3/02 ,  H03M3/00

CPC分类号： H03M3/32 ,  H03M3/376 ,  H03M3/43

摘要： A delta sigma modulator that has a low power dissipation without sacrificing modulator resolution includes, in one embodiment, a current mode digital to analog converter (DAC) in shunt with a conventional op amp in the first stage of the delta sigma modulator. By adding the current mode DAC in shunt with the first (or only) stage op amp of the delta sigma modulator, the slewing current needed during transients is provided by the combination of the op amp and DAC output signals. Since the DAC provides the slewing current required for the output signal change, the op amp need not apply the slewing current and therefore need only operate at low quiescent power.

摘要翻译： 在一个实施例中，具有低功耗而不牺牲调制器分辨率的ΔΣ调制器包括与ΔΣ调制器的第一级中的常规运算放大器分流的电流模式数模转换器（DAC）。 通过将电流模式DAC与Δ-Σ调制器的第一（或仅））级运算放大器并联，瞬态期间所需的回转电流由运算放大器和DAC输出信号的组合提供。 由于DAC提供输出信号变化所需的回转电流，因此运算放大器不需要使用回转电流，因此只需要在低静态功率下工作。