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公开(公告)号：US07084036B2
公开(公告)日：2006-08-01
申请号：US10972458
申请日：2004-10-26
Applicant: Yuan-Wei Zheng , Meng-Yu Pan , Julian Chang
Inventor： Yuan-Wei Zheng , Meng-Yu Pan , Julian Chang
IPC: H01L21/8236
CPC classification number: H01L27/11266 , H01L27/112
Abstract: A data writing method for mask read only memory using different doses of ion implantations to perform the data writing of Mask Read Only Memory. A semiconductor substrate having a plurality of gate structures is provided. The different ion implantations are performed depending on the mask from the user, thereby generating the different voltage output values. The different voltage output values are set as (00), (01), (10), and (11) for the bit output. Therefore, the present invention reduces the area of memory required for a specific data record, and lowers the production cost.
Abstract translation: 一种用于使用不同剂量的离子注入对仅读存储器进行掩模只读存储器的数据写入的数据写入方法。 提供具有多个栅极结构的半导体衬底。 根据用户的掩模执行不同的离子注入，从而产生不同的电压输出值。 对于位输出，不同的电压输出值被设置为（00），（01），（10）和（11）。 因此，本发明减少了特定数据记录所需的存储器面积，降低了生产成本。
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公开(公告)号：USD620875S1
公开(公告)日：2010-08-03
申请号：US29317330
申请日：2008-04-28
Applicant: Kevin Julian Chang , Peter A. Derenski
Designer： Kevin Julian Chang , Peter A. Derenski
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公开(公告)号：US07075843B2
公开(公告)日：2006-07-11
申请号：US10968102
申请日：2004-10-20
Applicant: Yuan Wei Zheng , Meng Yu Pan , Julian Chang
Inventor： Yuan Wei Zheng , Meng Yu Pan , Julian Chang
IPC: G11C7/00
Abstract: A sense amplifier for Mask Read Only Memory comprising a multiplexer, a plurality of comparators, a plurality of first selected transistors, and a plurality of second selected transistors. The gates of both first selected transistor and second selected transistor are connected to a word line select. One doping area of the first selected transistor is connected to the multiplexer for generating a plurality of signals, and another doping area is connected to a selected bit line. One doping area of each of the second selected transistor is connected to each of the comparators, and another doping area is connected to an external voltage. A cell voltage status is determined when each of the signals and one of doping areas of the second selected transistors are connected to each of the comparators.
Abstract translation: 一种用于掩模只读存储器的读出放大器，包括多路复用器，多个比较器，多个第一选择晶体管和多个第二选定晶体管。 第一选择晶体管和第二选择晶体管的栅极连接到字线选择。 第一选择的晶体管的一个掺杂区域连接到多路复用器以产生多个信号，并且另一个掺杂区域连接到所选择的位线。 第二选择晶体管中的每一个的一个掺杂区域连接到每个比较器，并且另一个掺杂区域连接到外部电压。 当每个信号和第二所选晶体管的掺杂区域中的每一个连接到每个比较器时，确定单元电压状态。
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公开(公告)号：US20050088880A1
公开(公告)日：2005-04-28
申请号：US10968102
申请日：2004-10-20
Applicant: Yuan Wei Zheng , Meng Yu Pan , Julian Chang
Inventor： Yuan Wei Zheng , Meng Yu Pan , Julian Chang
IPC: G11C5/00 , G11C7/06 , G11C7/14 , G11C17/10 , H01L27/112
Abstract: A sense amplifier for Mask Read Only Memory comprising a multiplexer, a plurality of comparators, a plurality of first selected transistors, and a plurality of second selected transistors. The gates of both first selected transistor and second selected transistor are connected to a word line select. One doping area of the first selected transistor is connected to the multiplexer for generating a plurality of signals, and another doping area is connected to a selected bit line. One doping area of each of the second selected transistor is connected to each of the comparators, and another doping area is connected to an external voltage. A cell voltage status is determined when each of the signals and one of doping areas of the second selected transistors are connected to each of the comparators.
Abstract translation: 一种用于掩模只读存储器的读出放大器，包括多路复用器，多个比较器，多个第一选择晶体管和多个第二选定晶体管。 第一选择晶体管和第二选择晶体管的栅极连接到字线选择。 第一选择的晶体管的一个掺杂区域连接到多路复用器以产生多个信号，并且另一个掺杂区域连接到所选择的位线。 第二选择晶体管中的每一个的一个掺杂区域连接到每个比较器，并且另一个掺杂区域连接到外部电压。 当每个信号和第二所选晶体管的掺杂区域中的每一个连接到每个比较器时，确定单元电压状态。
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公开(公告)号：US20050082633A1
公开(公告)日：2005-04-21
申请号：US10967131
申请日：2004-10-19
Applicant: Julian Chang , Yuanwei Zheng
Inventor： Julian Chang , Yuanwei Zheng
IPC: H01L21/82 , H01L21/8246 , H01L27/10 , H01L27/112 , H01L29/76
CPC classification number: H01L27/11253 , H01L27/112
Abstract: The present invention discloses a semiconductor structure avoiding the poly stringer formation in semiconductor processing. A semiconductor device is divided into a memory cell area and a peripheral portion. A plurality of parallel first isolation devices are positioned in the semiconductor substrate in the memory cell area. A second isolation device is positioned in the semiconductor substrate in the peripheral portion, and parallel with the first isolation device. A dummy buried doping region is positioned in the semiconductor substrate, and is positioned between the memory cell device and the peripheral portion and parallel with the second isolation device. An oxide area is formed on the dummy buried doping region. The dummy buried doping region and the oxide region can prevent poly string formation during subsequent processing.
Abstract translation: 本发明公开了一种在半导体处理中避免多晶硅层形成的半导体结构。 半导体器件被分成存储单元区域和周边部分。 多个平行的第一隔离器件位于存储单元区域中的半导体衬底中。 第二隔离装置位于周边部分的半导体衬底中，并与第一隔离装置平行。 虚设掩埋掺杂区域位于半导体衬底中，并位于存储单元器件与周边部分之间并与第二隔离器件平行。 在虚拟埋入掺杂区域上形成氧化物区域。 虚拟掩埋掺杂区域和氧化物区域可以防止后续处理期间的聚合物形成。
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公开(公告)号：US08329533B2
公开(公告)日：2012-12-11
申请号：US12781720
申请日：2010-05-17
Applicant: Julian Chang , An-Xing Shen , Soon-Won Kang
Inventor： Julian Chang , An-Xing Shen , Soon-Won Kang
IPC: H01L21/8242
CPC classification number: H01L27/105 , H01L27/11526 , H01L27/11531 , H01L28/60 , H01L29/94
Abstract: A stacked capacitor for double-poly flash memory is provided. The stacked capacitor is formed by a lower electrode, a lower dielectric layer, a central electrode, an upper dielectric layer, and an upper electrode, wherein the lower electrode is a doped region in a substrate. The manufacturing process of this stacked capacitor can be fully integrated in to the manufacturing process of the double-poly flash memory cell.
Abstract translation: 提供了一种用于双聚焦闪存的叠层电容器。 堆叠电容器由下电极，下电介质层，中心电极，上电介质层和上电极形成，其中下电极是衬底中的掺杂区域。 该叠层电容器的制造过程可以完全集成到双聚光闪存单元的制造过程中。
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公开(公告)号：US20110278656A1
公开(公告)日：2011-11-17
申请号：US12781720
申请日：2010-05-17
Applicant: Julian CHANG , An-Xing SHEN , Soon-Won KANG
Inventor： Julian CHANG , An-Xing SHEN , Soon-Won KANG
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/105 , H01L27/11526 , H01L27/11531 , H01L28/60 , H01L29/94
Abstract: A stacked capacitor for double-poly flash memory is provided. The stacked capacitor is formed by a lower electrode, a lower dielectric layer, a central electrode, an upper dielectric layer, and an upper electrode, wherein the lower electrode is a doped region in a substrate. The manufacturing process of this stacked capacitor can be fully integrated in to the manufacturing process of the double-poly flash memory cell.
Abstract translation: 提供了一种用于双聚焦闪存的叠层电容器。 堆叠电容器由下电极，下电介质层，中心电极，上电介质层和上电极形成，其中下电极是衬底中的掺杂区域。 该叠层电容器的制造过程可以完全集成到双聚光闪存单元的制造过程中。
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公开(公告)号：US20110233643A1
公开(公告)日：2011-09-29
申请号：US12729240
申请日：2010-03-23
Applicant: Julian CHANG
Inventor： Julian CHANG
IPC: H01L29/788
CPC classification number: G11C16/0425 , H01L27/11521 , H01L27/11524 , H01L29/66825 , H01L29/7881
Abstract: A two-transistor PMOS memory cell has a selective gate (SG) PMOS and a floating gate (FG) PMOS is provided. A control gate, overlapping the floating gate of the FG PMOS, of the memory cell is made by a polysilicon layer and located on an isolation structure.
Abstract translation: 双晶体管PMOS存储单元具有选择栅极（SG）PMOS和浮置栅极（FG）PMOS。 与存储单元的FG PMOS的浮置栅极重叠的控制栅极由多晶硅层制成并位于隔离结构上。
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公开(公告)号：US07221035B2
公开(公告)日：2007-05-22
申请号：US10967131
申请日：2004-10-19
Applicant: Julian Chang , YuanWei Zheng
Inventor： Julian Chang , YuanWei Zheng
IPC: H01L29/00
CPC classification number: H01L27/11253 , H01L27/112
Abstract: The present invention discloses a semiconductor structure avoiding the poly stringer formation in semiconductor processing. A semiconductor device is divided into a memory cell area and a peripheral portion. A plurality of parallel first isolation devices are positioned in the semiconductor substrate in the memory cell area. A second isolation device is positioned in the semiconductor substrate in the peripheral portion, and parallel with the first isolation device. A dummy buried doping region is positioned in the semiconductor substrate, and is positioned between the memory cell device and the peripheral portion and parallel with the second isolation device. An oxide area is formed on the dummy buried doping region. The dummy buried doping region and the oxide region can prevent poly string formation during subsequent processing.
Abstract translation: 本发明公开了一种在半导体处理中避免多晶硅层形成的半导体结构。 半导体器件被分成存储单元区域和周边部分。 多个平行的第一隔离器件位于存储单元区域中的半导体衬底中。 第二隔离装置位于周边部分的半导体衬底中，并与第一隔离装置平行。 虚设掩埋掺杂区域位于半导体衬底中，并且位于存储单元器件与周边部分之间并与第二隔离器件平行。 在虚拟埋入掺杂区域上形成氧化物区域。 虚拟掩埋掺杂区域和氧化物区域可以防止后续处理期间的聚合物形成。
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公开(公告)号：US20050090065A1
公开(公告)日：2005-04-28
申请号：US10972458
申请日：2004-10-26
Applicant: Yuan-Wei Zheng , Meng-Yu Pan , Julian Chang
Inventor： Yuan-Wei Zheng , Meng-Yu Pan , Julian Chang
IPC: G11C13/04 , H01L21/336 , H01L21/8234 , H01L21/8236 , H01L21/8246 , H01L27/04 , H01L27/112
CPC classification number: H01L27/11266 , H01L27/112
Abstract: A data writing method for mask read only memory using different doses of ion implantations to perform the data writing of Mask Read Only Memory. A semiconductor substrate having a plurality of gate structures is provided. The different ion implantations are performed depending on the mask from the user, thereby generating the different voltage output values. The different voltage output values are set as (00), (01), (10), and (11) for the bit output. Therefore, the present invention reduces the area of memory required for a specific data record, and lowers the production cost.
Abstract translation: 一种用于使用不同剂量的离子注入对仅读存储器进行掩模只读存储器的数据写入的数据写入方法。 提供具有多个栅极结构的半导体衬底。 根据用户的掩模执行不同的离子注入，从而产生不同的电压输出值。 对于位输出，不同的电压输出值被设置为（00），（01），（10）和（11）。 因此，本发明减少了特定数据记录所需的存储器面积，降低了生产成本。
