公开(公告)号：US5787025A

公开(公告)日：1998-07-28

申请号：US607937

申请日：1996-02-28

申请人： Jumana A. Muwafi ,  Mihran Touriguian

发明人： Jumana A. Muwafi ,  Mihran Touriguian

IPC分类号： G06F7/00 ,  G06F7/48 ,  G06F7/76 ,  G06F7/38

CPC分类号： G06F7/48 ,  G06F2207/3816 ,  G06F2207/3892

摘要： A circuit for performing either single precision or double precision arithmetic operations on data, a system including such a circuit, and a method implemented by the system. Preferably, the circuit is an arithmetic manipulation unit (AMU) which performs arithmetic operations on N-bit words in a single precision mode and on 2N-bit words in a double precision mode. The AMU concatenates two N-bit words in the double precision mode thus producing a 2N-bit operand, and performs a selected one of several arithmetic operations on the operand and a second 2N-bit operand. Preferably, the AMU performs a double precision operation in two cycles: a first cycle generating a first operand and loading the operand to an output register; and a second cycle in which a second operand is generated from a second pair of N-bit parts from the memory, the first operand is fed back from the output register, and an arithmetic operation is performed on the two operands. The system preferably includes a multi-port memory, executes instructions in pipelined fashion, and operates in a single precision mode to fetch two N-bit operands from the memory in a single pipeline cycle using two address pointers and in a double precision mode to fetch two N-bit words from the memory in a single cycle. In a double precision mode, the system can fetch two N-bit parts stored in consecutive memory locations in a single cycle, by generating and asserting to the memory two addresses in response to one address pointer.

摘要翻译： 用于对数据执行单精度或双精度算术运算的电路，包括这种电路的系统以及由该系统实现的方法。 优选地，电路是以单精度模式对N位字执行算术运算的算术运算单元（AMU），以双精度模式对2N位字执行算术运算。 AMU以双精度模式连接两个N位字，从而产生2N位操作数，并对操作数和第2N位操作数执行若干算术运算中选择的一个运算。 优选地，AMU在两个周期中执行双精度操作：第一周期产生第一操作数并将操作数加载到输出寄存器; 以及第二周期，其中从存储器从第二对N位部分生成第二操作数，第一操作数从输出寄存器反馈，并且对两个操作数执行算术运算。 该系统优选地包括多端口存储器，以流水线方式执行指令，并以单精度模式操作，以使用两个地址指针在单个流水线周期中从存储器中获取两个N位操作数，并且以双精度模式获取 在单个周期内从内存中的两个N位字。 在双精度模式下，系统可以通过针对一个地址指针产生和断言给存储器两个地址，从而在一个周期内获取存储在连续存储单元中的两个N位元件。

公开(公告)号：US5978822A

公开(公告)日：1999-11-02

申请号：US581047

申请日：1995-12-29

申请人： Jumana A. Muwafi ,  Gerhard Fettweis ,  Howard W. Neff

发明人： Jumana A. Muwafi ,  Gerhard Fettweis ,  Howard W. Neff

IPC分类号： G06F5/01 ,  G06F7/76 ,  G06F7/00

CPC分类号： G06F7/762 ,  G06F5/015 ,  G06F7/768

摘要： A circuit having a single branch, which is controllable to implement either a left or right shift of bits of a data word. Preferably, the circuit is controllable to implement any selected one of the following operations: a left or right shift of bits of the word; and rotation (to the left or right) of bits of the word. In a preferred implementation, the circuit includes a set of multiplexer stages and circuitry for selectively inverting the order of the bits of the word input to, and the word output from, the set of multiplexer stages. Each of the multiplexer stages shifts the bits of the word it receives either by zero bits (in response to a first control signal), or by a positive number of bits (in response to a second control signal). By selectively controlling various subsets of the multiplexer stages, the bits of the input word can be shifted by any of a number of places (from zero to N, where N is some positive number). In another aspect, the invention is a circuit for rotating bits of an input word (by two or more bits to the left or right) during a single cycle, by duplicating the input word to form an extended word, shifting bits of the extended word, and selecting a subset of the shifted bits of the extended word. Other aspects of the invention are methods performed by, and a digital signal processor including, either embodiment of the inventive circuit.

摘要翻译： 具有单个分支的电路，其可控制以实现数据字的位的左移或右移。 优选地，电路是可控制的，以实现以下操作中的任何选择的一个：字的位的左移或右移; 以及字的位的旋转（向左或向右）。 在优选的实施方案中，电路包括一组多路复用器级和电路，用于选择性地反转字输入的位的顺序和多路复用器级的集合输出的字。 多路复用器级中的每一个通过零位（响应于第一控制信号）或通过正数位（响应于第二控制信号）来移位其接收的字的位。 通过选择性地控制多路复用器级的各个子集，可以通过多个位置（从零到N，其中N是一些正数）中的任意一个来移位输入字的位。 另一方面，本发明是一种电路，用于在单个周期期间通过复制输入字以形成扩展字来转换输入字的位（向左或向右两位或更多位），从而使扩展字的位移位 ，并且选择扩展字的移位位的子集。 本发明的其他方面是由本发明的电路的任一实施例执行的方法和数字信号处理器。