公开(公告)号：US20130242201A1

公开(公告)日：2013-09-19

申请号：US13599113

申请日：2012-08-30

申请人： Jun DEGUCHI ,  Hideaki Majima ,  Yuichi Nakamura ,  Hisao Kawasato ,  Nau Ozaki ,  Toshiyuki Yamagishi

发明人： Jun DEGUCHI ,  Hideaki Majima ,  Yuichi Nakamura ,  Hisao Kawasato ,  Nau Ozaki ,  Toshiyuki Yamagishi

IPC分类号： H04N5/40

CPC分类号： H04N5/40 ,  H04N7/025 ,  H04N7/08 ,  H04N21/41407 ,  H04N21/4722

摘要： According to one embodiment, a transmission system includes a transmitter, and a receiver. The transmitter includes one or a plurality of light sources, a modulator, a first driver, a display, and a second driver. The one or a plurality of light sources is configured to emit a visible light whose light amount corresponds to a first drive signal. The modulator is configured to, according to transmission data to be transmitted from the transmitter to the receiver, modulate a first luminance signal indicative of an amount of the light the light source is configured to emit, to generate a second luminance signal. The first driver is configured to generate the first drive signal based on the second luminance signal. A mean of the second luminance signal during one frame in the input video signal is substantially equal to a value of the first luminance signal in the frame.

摘要翻译： 根据一个实施例，传输系统包括发射机和接收机。 发射机包括一个或多个光源，调制器，第一驱动器，显示器和第二驱动器。 一个或多个光源被配置为发射其光量对应于第一驱动信号的可见光。 调制器被配置为根据要从发射机发射到接收机的传输数据，调制指示光源被配置为发射的光量的第一亮度信号，以产生第二亮度信号。 第一驱动器被配置为基于第二亮度信号产生第一驱动信号。 输入视频信号中的一帧期间的第二亮度信号的平均值基本上等于帧中第一亮度信号的值。

公开(公告)号：US08451965B2

公开(公告)日：2013-05-28

申请号：US13053396

申请日：2011-03-22

申请人： Jun Deguchi ,  Daisuke Miyashita ,  Hiroyuki Kobayashi

发明人： Jun Deguchi ,  Daisuke Miyashita ,  Hiroyuki Kobayashi

IPC分类号： H03D1/04 ,  H03D1/06 ,  H03K5/01 ,  H03K6/04 ,  H04B1/10 ,  H04L1/00 ,  H04L25/08

CPC分类号： H03L7/1803 ,  H03L2207/50 ,  H04L27/0014 ,  H04L2027/0053 ,  H04L2027/0069

摘要： According to one embodiment, a semiconductor integrated device includes a digitally controlled oscillator, a counter, a time to digital converter, an adder, and a control signal generator. The time to digital converter includes a frequency-divider, a plurality of impedance elements, and a phase difference detector. The frequency-divider is configured to frequency-divide the oscillation signal to generate a plurality of frequency-divided signals. The plurality of impedance elements is configured to voltage-divide the frequency-divided signals to generate a plurality of delay signals of the oscillation signal. The phase difference detector is configured to output the third digital signal corresponding to the phase difference between the reference signal and the oscillation signal by comparing the reference signal with each of the delay signals.

摘要翻译： 根据一个实施例，半导体集成器件包括数字控制振荡器，计数器，时间到数字转换器，加法器和控制信号发生器。 数字转换器的时间包括分频器，多个阻抗元件和相位差检测器。 分频器被配置为对振荡信号进行分频以产生多个分频信号。 多个阻抗元件被配置为对分频信号进行分压以产生振荡信号的多个延迟信号。 相位差检测器被配置为通过将参考信号与每个延迟信号进行比较来输出与参考信号和振荡信号之间的相位差相对应的第三数字信号。

公开(公告)号：US08362820B2

公开(公告)日：2013-01-29

申请号：US13397742

申请日：2012-02-16

申请人： Jun Deguchi ,  Daisuke Miyashita

发明人： Jun Deguchi ,  Daisuke Miyashita

IPC分类号： H04B1/40 ,  H04B1/26

CPC分类号： H03B19/14

摘要： A semiconductor integrated circuit includes a mixer circuit unit having a first single gate mixer configured to receive a first input signal having a first frequency and a second input signal having a second frequency as inputs, a second single gate mixer configured to receive the first input signal and a third input signal of a phase inverted from a phase of the second input signal as inputs, a third single gate mixer configured to receive a fourth input signal of a phase inverted from the phase of the first input signal and the second input signal as inputs, and a fourth single gate mixer configured to receive the third and the fourth input signals as inputs; and a ½-frequency divider unit configured to receive output signals from the first to the fourth single gate mixers as inputs and output a desired signal.

摘要翻译： 半导体集成电路包括具有第一单栅极混频器的混频器电路单元，其被配置为接收具有第一频率的第一输入信号和具有第二频率的第二输入信号作为输入;第二单门混频器，被配置为接收第一输入信号 以及从所述第二输入信号的相位反转的相位的第三输入信号作为输入;第三单门混频器，被配置为接收从所述第一输入信号和所述第二输入信号的相位反相的相位的第四输入信号， 配置为接收第三和第四输入信号作为输入的第四单门混频器; 以及1/2分频器单元，被配置为从第一至第四单个栅极混合器接收输出信号作为输入并输出期望的信号。

公开(公告)号：US08233874B2

公开(公告)日：2012-07-31

申请号：US13370101

申请日：2012-02-09

申请人： Jun Deguchi ,  Shouhei Kousai ,  Daisuke Miyashita

发明人： Jun Deguchi ,  Shouhei Kousai ,  Daisuke Miyashita

IPC分类号： H04B15/00

CPC分类号： H04B1/0053

摘要： A wireless communication apparatus includes a local oscillator that generates a plurality of LO (Local Oschillation) signals corresponding to frequencies of a plurality of input RF (Radio Frequency) signals, an accumulator that accumulates the plurality of LO signals generated by the local oscillator to generate an accumulated signal, a mixer that mixes the plurality of RF signals and the accumulated signal generated by the accumulator and to generate a plurality of base band signals, and a first signal processing unit that executes a signal process with respect to the plurality of base band signals generated by the mixer.

摘要翻译： 无线通信装置包括本地振荡器，其产生对应于多个输入RF（射频）信号的频率的多个LO（局部烧灼）信号，累加器，其累积由本地振荡器产生的多个LO信号，以产生 累积信号，混合多个RF信号的混频器和由累加器产生的累加信号并产生多个基带信号;以及第一信号处理单元，其执行关于多个基带的信号处理 由混合器产生的信号。

公开(公告)号：US20120142292A1

公开(公告)日：2012-06-07

申请号：US13370101

申请日：2012-02-09

申请人： Jun DEGUCHI ,  Shouhei Kousai ,  Daisuke Miyashita

发明人： Jun DEGUCHI ,  Shouhei Kousai ,  Daisuke Miyashita

IPC分类号： H04B1/04

CPC分类号： H04B1/0053

摘要： A wireless communication apparatus includes a local oscillator that generates a plurality of LO (Local Oschillation) signals corresponding to frequencies of a plurality of input RF (Radio Frequency) signals, an accumulator that accumulates the plurality of LO signals generated by the local oscillator to generate an accumulated signal, a mixer that mixes the plurality of RF signals and the accumulated signal generated by the accumulator and to generate a plurality of base band signals, and a first signal processing unit that executes a signal process with respect to the plurality of base band signals generated by the mixer.

摘要翻译： 无线通信装置包括本地振荡器，其产生对应于多个输入RF（射频）信号的频率的多个LO（局部烧灼）信号，累加器，其累积由本地振荡器产生的多个LO信号，以产生 累积信号，混合多个RF信号的混频器和由累加器产生的累加信号并产生多个基带信号;以及第一信号处理单元，其执行关于多个基带的信号处理 由混合器产生的信号。

公开(公告)号：US20120112840A1

公开(公告)日：2012-05-10

申请号：US13354757

申请日：2012-01-20

申请人： Jun DEGUCHI ,  Naoki Kobayashi

发明人： Jun DEGUCHI ,  Naoki Kobayashi

IPC分类号： H03F3/04 ,  H03F1/22

CPC分类号： H03F3/3028 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/505 ,  H03F2200/453 ,  H03F2203/45236 ,  H03F2203/45244 ,  H03F2203/45394 ,  H03F2203/45508 ,  H03F2203/45528 ,  H03F2203/45544 ,  H03F2203/45696 ,  H03F2203/45698 ,  H03F2203/45702

摘要： A semiconductor integrated circuit device constituting an inverting amplifier employs a cascode current source as a current source. In the semiconductor integrated circuit device, a high-potential-side transistor of the cascode current source and a low-potential-side transistor constituting an amplification portion are shared. The configuration can not only make an output impedance of the cascode current source high and improve current source characteristics but also make a minimum potential at a minimum potential point of the amplification portion low and ensure a sufficient power supply voltage margin.

摘要翻译： 构成反相放大器的半导体集成电路器件采用共源共栅电流源作为电流源。 在半导体集成电路器件中，共享共源共栅电流源的高电位侧晶体管和构成放大部分的低电位侧晶体管。 该配置不仅可以使共源共栅电流源的输出阻抗高，并且提高电流源特性，而且使放大部分的最小电位处的最小电位降低，并确保足够的电源电压裕度。

公开(公告)号：US08149055B2

公开(公告)日：2012-04-03

申请号：US13231562

申请日：2011-09-13

申请人： Jun Deguchi ,  Naoki Kobayashi

发明人： Jun Deguchi ,  Naoki Kobayashi

IPC分类号： H03F3/45 ,  H03F3/04

CPC分类号： H03F3/3028 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/505 ,  H03F2200/453 ,  H03F2203/45236 ,  H03F2203/45244 ,  H03F2203/45394 ,  H03F2203/45508 ,  H03F2203/45528 ,  H03F2203/45544 ,  H03F2203/45696 ,  H03F2203/45698 ,  H03F2203/45702

摘要： A semiconductor integrated circuit device constituting an inverting amplifier employs a cascode current source as a current source. In the semiconductor integrated circuit device, a high-potential-side transistor of the cascode current source and a low-potential-side transistor constituting an amplification portion are shared. The configuration can not only make an output impedance of the cascode current source high and improve current source characteristics but also make a minimum potential at a minimum potential point of the amplification portion low and ensure a sufficient power supply voltage margin.

摘要翻译： 构成反相放大器的半导体集成电路器件采用共源共栅电流源作为电流源。 在半导体集成电路器件中，共享共源共栅电流源的高电位侧晶体管和构成放大部分的低电位侧晶体管。 该配置不仅可以使共源共栅电流源的输出阻抗高，并且提高电流源特性，而且使放大部分的最小电位处的最小电位降低，并确保足够的电源电压裕度。

公开(公告)号：US20120001696A1

公开(公告)日：2012-01-05

申请号：US13231562

申请日：2011-09-13

申请人： Jun DEGUCHI ,  Naoki KOBAYASHI

发明人： Jun DEGUCHI ,  Naoki KOBAYASHI

IPC分类号： H03F3/16

CPC分类号： H03F3/3028 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/505 ,  H03F2200/453 ,  H03F2203/45236 ,  H03F2203/45244 ,  H03F2203/45394 ,  H03F2203/45508 ,  H03F2203/45528 ,  H03F2203/45544 ,  H03F2203/45696 ,  H03F2203/45698 ,  H03F2203/45702

摘要： A semiconductor integrated circuit device constituting an inverting amplifier employs a cascode current source as a current source. In the semiconductor integrated circuit device, a high-potential-side transistor of the cascode current source and a low-potential-side transistor constituting an amplification portion are shared. The configuration can not only make an output impedance of the cascode current source high and improve current source characteristics but also make a minimum potential at a minimum potential point of the amplification portion low and ensure a sufficient power supply voltage margin.

公开(公告)号：US20090318096A1

公开(公告)日：2009-12-24

申请号：US12489860

申请日：2009-06-23

申请人： Jun Deguchi ,  Daisuke Miyashita ,  Hideyuki Kokatsu

发明人： Jun Deguchi ,  Daisuke Miyashita ,  Hideyuki Kokatsu

IPC分类号： H04B1/38 ,  H01L25/00

CPC分类号： H04B1/04 ,  H04B2001/0491

摘要： A semiconductor integrated circuit includes a first input terminal configured to input a baseband signal, a second input terminal configured to input a local oscillation signal, an output terminal configured to output a modulating signal, a first amplifier circuit configured to receive the baseband signal through the first input terminal and to output a first amplified signal of the baseband signal, a 2-multiplying circuit configured to receive the local oscillation signal through the second input terminal and to output a 2-multiplied signal of the local oscillation signal, an adder configured to add the 2-multiplied signal and the first amplified signal and to output an addition signal, a second amplifier circuit configured to receive the addition signal and to output a second amplified signal of the addition signal, and a mixer configured to multiply the second amplified signal and the local oscillation signal and to output the modulating signal to the output terminal.

摘要翻译： 半导体集成电路包括被配置为输入基带信号的第一输入端子，被配置为输入本地振荡信号的第二输入端子，被配置为输出调制信号的输出端子，被配置为通过所述第一输入端子接收基带信号的第一放大器电路 第一输入端并输出基带信号的第一放大信号; 2倍增电路，被配置为通过第二输入端接收本地振荡信号，并输出本地振荡信号的2相乘信号;加法器，被配置为 添加2倍增信号和第1放大信号并输出​​加法信号;第2放大电路，被配置为接收相加信号并输出​​加法信号的第2放大信号;以及混频器，被配置为将第2放大信号 和本地振荡信号，并将调制信号输出到输出端。

公开(公告)号：US09245621B2

公开(公告)日：2016-01-26

申请号：US14118703

申请日：2012-03-09

申请人： Jun Deguchi ,  Haruki Toda

发明人： Jun Deguchi ,  Haruki Toda

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2013/0073 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/77

摘要： A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括设置在多个第一线和多条第二线的交点处的多个存储单元; 和写电路。 写入电路在执行写入操作时执行第一步骤，跨连接到数据写入目标的选择的存储器单元的第一和第二线路施加电压，并跨越连接到第一和第二线路的不同电压 所述多个存储单元的数据写未指定的未选择的存储单元，并且在执行所述第一步骤之后，执行第二步骤，在连接到所选存储单元的第一和第二行上施加数据写入所需的电压 并且将连接到未选择的存储单元的第一和第二线中的至少一个引入浮动状态。