公开(公告)号：US09252291B2

公开(公告)日：2016-02-02

申请号：US13070108

申请日：2011-03-23

申请人： Jun Fujiki ,  Naoki Yasuda ,  Daisuke Matsushita

发明人： Jun Fujiki ,  Naoki Yasuda ,  Daisuke Matsushita

IPC分类号： H01L29/08 ,  H01L29/792 ,  G11C16/04 ,  H01L27/115

CPC分类号： H01L29/792 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first memory portion. The first memory portion includes a first base semiconductor layer, a first electrode, a first channel semiconductor layer, a first base tunnel insulating film, a first channel tunnel insulating, a first charge retention layer and a first block insulating film. The first channel semiconductor layer is provided between the first base semiconductor layer and the first electrode, and includes a first channel portion. The first base tunnel insulating film is provided between the first base semiconductor layer and the first channel semiconductor layer. The first channel tunnel insulating film is provided between the first electrode and the first channel portion. The first charge retention layer is provided between the first electrode and the first channel tunnel insulating film. The first block insulating film is provided between the first electrode and the first charge retention layer.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一存储器部分。 第一存储部分包括第一基极半导体层，第一电极，第一沟道半导体层，第一基极隧道绝缘膜，第一沟道隧道绝缘，第一电荷保持层和第一块绝缘膜。 第一沟道半导体层设置在第一基底半导体层和第一电极之间，并且包括第一沟道部分。 第一基极隧道绝缘膜设置在第一基极半导体层和第一沟道半导体层之间。 第一通道隧道绝缘膜设置在第一电极和第一沟道部分之间。 第一电荷保持层设置在第一电极和第一沟道隧道绝缘膜之间。 第一块绝缘膜设置在第一电极和第一电荷保持层之间。

公开(公告)号：US08921920B2

公开(公告)日：2014-12-30

申请号：US13418620

申请日：2012-03-13

申请人： Shigeru Kawanaka ,  Kosuke Tatsumura ,  Naoki Yasuda ,  Jun Fujiki ,  Atsushi Kawasumi

发明人： Shigeru Kawanaka ,  Kosuke Tatsumura ,  Naoki Yasuda ,  Jun Fujiki ,  Atsushi Kawasumi

IPC分类号： H01L29/792 ,  H01L21/28 ,  G11C11/22 ,  G11C11/412 ,  G11C14/00 ,  H01L29/51 ,  H01L27/11 ,  H01L27/115 ,  H01L27/118

CPC分类号： H01L21/28282 ,  G11C11/22 ,  G11C11/412 ,  G11C14/0081 ,  H01L27/1104 ,  H01L27/1156 ,  H01L27/11568 ,  H01L27/11807 ,  H01L29/518 ,  H01L29/792

摘要： A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.

摘要翻译： 半导体器件具有半导体衬底和半导体衬底上具有FET的半导体元件，并且包括根据OFF状态和ON状态的不同阈值电压。 半导体元件具有设置在形成半导体基板的沟道的部分上方的绝缘膜，设置在绝缘膜上方的栅电极和设置在绝缘膜和栅电极之间的电荷陷阱膜，并且交换更多的电子 栅电极与通道相比。

公开(公告)号：US08901635B2

公开(公告)日：2014-12-02

申请号：US13414988

申请日：2012-03-08

申请人： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Tomoko Fujiwara

发明人： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Tomoko Fujiwara

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66833

摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, an insulating film, and a charge storage film. The stacked body includes a plurality of electrode films stacked with an inter-layer insulating film provided between the electrode films. The semiconductor pillar pierces the stacked body. The insulating film is provided between the semiconductor pillar and the electrode films on an outer side of the semiconductor pillar with a gap interposed. The charge storage film is provided between the insulating film and the electrode films. The semiconductor pillar includes germanium. An upper end portion of the semiconductor pillar is supported by an interconnect provided above the stacked body.

摘要翻译： 根据一个实施例，半导体存储器件包括堆叠体，半导体柱，绝缘膜和电荷存储膜。 层叠体包括层叠了设置在电极膜之间的层间绝缘膜的多个电极膜。 半导体柱穿透层叠体。 绝缘膜设置在半导体柱和位于半导体柱的外侧的电极膜之间，间隙插入。 电荷存储膜设置在绝缘膜和电极膜之间。 半导体柱包括锗。 半导体柱的上端部由设置在层叠体上方的配线支撑。

公开(公告)号：US20130234231A1

公开(公告)日：2013-09-12

申请号：US13560260

申请日：2012-07-27

申请人： Jun FUJIKI ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Jun FUJIKI ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66833

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a stacked body, a second insulating layer, a select gate, a memory hole, a memory film, a channel body, a first semiconductor layer, and a second semiconductor layer. The select gate is provided on the second insulating layer. The memory film is provided on an inner wall of the memory hole. The channel body is provided inside the memory film. The first semiconductor layer is provided on an upper surface of the channel body. The second semiconductor layer is provided on the first semiconductor layer. The first semiconductor layer contains silicon germanium. The second semiconductor layer contains silicon germanium doped with a first impurity. A boundary between the first semiconductor layer and the second semiconductor layer is provided above a position of an upper end of the select gate.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括层叠体，第二绝缘层，选择栅极，存储器孔，存储​​膜，通道体，第一半导体层和第二半导体层。 选择栅极设置在第二绝缘层上。 记忆膜设置在存储孔的内壁上。 通道体设置在记忆膜的内部。 第一半导体层设置在通道主体的上表面上。 第二半导体层设置在第一半导体层上。 第一半导体层包含硅锗。 第二半导体层包含掺杂有第一杂质的硅锗。 第一半导体层和第二半导体层之间的边界设置在选择栅极的上端的位置的上方。

公开(公告)号：US20130062681A1

公开(公告)日：2013-03-14

申请号：US13414988

申请日：2012-03-08

申请人： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Tomoko Fujiwara

发明人： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Tomoko Fujiwara

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66833

摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, an insulating film, and a charge storage film. The stacked body includes a plurality of electrode films stacked with an inter-layer insulating film provided between the electrode films. The semiconductor pillar pierces the stacked body. The insulating film is provided between the semiconductor pillar and the electrode films on an outer side of the semiconductor pillar with a gap interposed. The charge storage film is provided between the insulating film and the electrode films. The semiconductor pillar includes germanium. An upper end portion of the semiconductor pillar is supported by an interconnect provided above the stacked body.

摘要翻译： 根据一个实施例，半导体存储器件包括堆叠体，半导体柱，绝缘膜和电荷存储膜。 层叠体包括层叠了设置在电极膜之间的层间绝缘膜的多个电极膜。 半导体柱穿透层叠体。 绝缘膜设置在半导体柱和位于半导体柱的外侧的电极膜之间，间隙插入。 电荷存储膜设置在绝缘膜和电极膜之间。 半导体柱包括锗。 半导体柱的上端部由设置在层叠体上方的配线支撑。

公开(公告)号：US20130008685A1

公开(公告)日：2013-01-10

申请号：US13543344

申请日：2012-07-06

申请人： Kiichiro MATSUSHITA ,  Hiroomi HANAI ,  Kazunori HAYASHI ,  Jun FUJIKI ,  Akihiro OOHASHI ,  Kayoko TAKAYANAGI ,  Kazumasa MUKOBATA

发明人： Kiichiro MATSUSHITA ,  Hiroomi HANAI ,  Kazunori HAYASHI ,  Jun FUJIKI ,  Akihiro OOHASHI ,  Kayoko TAKAYANAGI ,  Kazumasa MUKOBATA

IPC分类号： H01B7/00 ,  H01B17/00

CPC分类号： H01B3/46

摘要： Provided is a covering material, which includes a backing having an upper surface and a lower surface opposite to the upper surface, and a viscoelastic layer formed on the upper surface of the backing, in which the covering material is a covering material for covering a rectangular electric wire, and an adhesive force of the viscoelastic layer to the lower surface of the backing as measured by peeling at a peeling angle of 180° and a tensile rate of 300 mm/min is 0.05 N/20 mm or more and 10 N/20 mm or less. A covered rectangular electric wire includes the covering material and a rectangular electric wire covered with the covering material. An electrical device is produced by using the covered rectangular electric wire.

摘要翻译： 提供一种覆盖材料，其包括具有上表面和与上表面相对的下表面的背衬，以及形成在背衬的上表面上的粘弹性层，其中覆盖材料是用于覆盖矩形的覆盖材料 电线以及通过在180°的剥离角度和300mm / min的拉伸速度下剥离测定的粘弹性层对背衬的下表面的粘合力为0.05N / 20mm以上且10N / 20mm以下。 覆盖的矩形电线包括覆盖材料和覆盖有覆盖材料的矩形电线。 通过使用覆盖的矩形电线制造电气设备。

公开(公告)号：US08267782B2

公开(公告)日：2012-09-18

申请号：US12601541

申请日：2008-11-14

申请人： Tatsuya Suzuki ,  Jun Fujiki ,  Takanori Kikuchi

发明人： Tatsuya Suzuki ,  Jun Fujiki ,  Takanori Kikuchi

IPC分类号： G06F17/00

CPC分类号： A63F13/525 ,  A63F13/422 ,  A63F13/5255 ,  A63F13/56 ,  A63F13/63 ,  A63F13/822 ,  G06T15/20 ,  G06T19/00

摘要： A game device includes a shape data storage which stores data of an object disposed in a three-dimensional space, a first rendering unit which sets a point of view and a line of sight and renders the object by referencing data stored in the shape data storage, a viewpoint changing unit which receives a change instruction indicating a change of the point of view or line of sight and changes the point of view or line of sight. The viewpoint changing unit changes the point of view or line of sight to outside a predetermined range when the point of view or line of sight enters within the predetermined range.

摘要翻译： 一种游戏装置，包括存储设置在三维空间中的物体的数据的形状数据存储器，设置观察点和视线的第一渲染单元，并且通过参考存储在形状数据存储器中的数据来呈现对象 视点改变单元，其接收指示视点或视线的变化并改变视点或视线的改变指令。 当观察点或视线进入预定范围内时，视点改变单元将视点或视线改变到预定范围之外。

公开(公告)号：US20120075928A1

公开(公告)日：2012-03-29

申请号：US13246996

申请日：2011-09-28

申请人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

发明人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

IPC分类号： H01L29/792 ,  G11C11/34 ,  G11C11/412

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L27/11568 ,  H01L29/4234

摘要： In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i−1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.

摘要翻译： 在半导体层中，通过向第一电极施加第一电位，向所有背栅电极施加低于第一电位的第二电位，向第一电极施加高于第一电位的第三电位，写入信息 到（i-1）个前栅电极，并且将第二和第三电位之间的第四电位施加到第i个和后续的前栅电极，其中“i”是正整数，并且识别信息的特定位置 要写

公开(公告)号：US20120032248A1

公开(公告)日：2012-02-09

申请号：US13272821

申请日：2011-10-13

申请人： Masao SHINGU ,  Jun Fujiki ,  Naoki Yasuda ,  Koichi Muraoka

发明人： Masao SHINGU ,  Jun Fujiki ,  Naoki Yasuda ,  Koichi Muraoka

IPC分类号： H01L29/792 ,  H01L29/788

CPC分类号： H01L29/7883 ,  G11C11/40 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/788 ,  H01L29/792

摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储元件，包括：半导体衬底，包括：源极区; 漏区; 和通道区域; 形成在沟道区上的下绝缘膜; 电荷存储膜，形成在下绝缘膜上并存储数据; 形成在电荷存储膜上的上绝缘膜; 以及形成在所述上绝缘膜上的控制栅极，其中所述上绝缘膜包括：第一绝缘膜; 以及与所述第一绝缘膜层压的第二绝缘膜，并且其中所述第一绝缘膜形成为具有比所述第二绝缘膜的陷阱级密度大的陷阱级密度。

公开(公告)号：US07961524B2

公开(公告)日：2011-06-14

申请号：US12053108

申请日：2008-03-21

申请人： Jun Fujiki

发明人： Jun Fujiki

IPC分类号： G11C11/04

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483

摘要： A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device has source/drain diffusion layers spaced from each other in a surface portion of a semiconductor substrate, a laminated insulating film formed on a channel between the source/drain diffusion layers and including a charge storage layer, and a gate electrode formed on the laminated insulating film, the nonvolatile semiconductor memory device changing its data memory state by injection of charges into the charge storage layer. The method includes, before injecting charges to change the data memory state into the charge storage layer: injecting charges having a polarity identical to that of the charges to be injected; and further injecting charges having a polarity opposite to that of the injected charges.

摘要翻译： 提供一种用于驱动非易失性半导体存储器件的方法。 非易失性半导体存储器件在半导体衬底的表面部分中具有彼此间隔开的源极/漏极扩散层，形成在源极/漏极扩散层之间并且包括电荷存储层的沟道上的层叠绝缘膜，以及栅电极 形成在层叠绝缘膜上的非易失性半导体存储器件通过将电荷注入电荷存储层来改变其数据存储状态。 该方法包括：在注入电荷以将数据存储状态改变为电荷存储层之前，注入具有与要注入的电荷相同极性的电荷; 并且进一步注入与注入的电荷的极性相反极性的电荷。