公开(公告)号：US09728481B2

公开(公告)日：2017-08-08

申请号：US13227328

申请日：2011-09-07

申请人： Abraham F. Yee ,  Joe Greco ,  Jun Zhai ,  Joseph Minacapelli ,  John Y. Chen

发明人： Abraham F. Yee ,  Joe Greco ,  Jun Zhai ,  Joseph Minacapelli ,  John Y. Chen

IPC分类号： H01L23/10 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

CPC分类号： H01L23/36 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/00012

摘要： An IC system includes low-power chips, e.g., memory chips, located proximate one or more higher power chips, e.g., logic chips, without suffering the effects of overheating. The IC system may include a high-power chip disposed on a packaging substrate and a low-power chip embedded in the packaging substrate to form a stack. Because portions of the packaging substrate thermally insulate the low-power chip from the high-power chip, the low-power chip can be embedded in the IC system in close proximity to the high-power chip without being over heated by the high-power chip. Such close proximity between the low-power chip and the high-power chip advantageously shortens the path length of interconnects therebetween, which improves device performance and reduces interconnect parasitics in the IC system.

公开(公告)号：US20140061950A1

公开(公告)日：2014-03-06

申请号：US13605263

申请日：2012-09-06

申请人： Jun Zhai

发明人： Jun Zhai

IPC分类号： H01L23/522 ,  H01L21/50

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161

摘要： In one embodiment, an electronic memory module may be provided to couple two or more stacked memory dies. The memory module may include a first substrate that couples the first memory die in a flip chip configuration. The substrate also includes connectors to couple to a second substrate, which has a flip chip connection to a second memory die. A surface of the first substrate opposite the flip chip connection of the first memory die may include connectors to couple to the first memory die (through the first substrate) and may include connectors to couple to the second memory die (through the connectors that couple to the second substrate, and through the first substrate.

摘要翻译： 在一个实施例中，可以提供电子存储器模块以耦合两个或更多个堆叠的存储器管芯。 存储器模块可以包括以倒装芯片配置耦合第一存储管芯的第一衬底。 衬底还包括连接到第二衬底的连接器，第二衬底具有到第二存储器管芯的倒装芯片连接。 与第一存储器管芯的倒装芯片连接相对的第一衬底的表面可以包括连接到第一存储器管芯（通过第一衬底）的连接器，并且可以包括连接到第二存储器管芯的连接器（通过连接到 第二基板，并通过第一基板。

公开(公告)号：US20130020702A1

公开(公告)日：2013-01-24

申请号：US13188287

申请日：2011-07-21

申请人： Jun Zhai ,  Vincent R. von Kaenel

发明人： Jun Zhai ,  Vincent R. von Kaenel

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1713 ,  H01L2224/4824 ,  H01L2224/81815 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15321 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： Semiconductor device modules having two or more integrated circuit dies mounted on opposing sides of a substrate. The integrated circuit dies are mounted by use of surface mount connections, such as flip chip connections implemented using conductive bumps. Systems may include one or more of the present semiconductor device modules, and in some cases may also include other modules, such as a system module.

摘要翻译： 具有安装在基板的相对侧上的两个或多个集成电路管芯的半导体器件模块。 集成电路管芯通过使用表面安装连接来安装，例如使用导电凸块实现的倒装芯片连接。 系统可以包括一个或多个当前的半导体器件模块，并且在一些情况下还可以包括其他模块，诸如系统模块。

公开(公告)号：US08301668B1

公开(公告)日：2012-10-30

申请号：US12105936

申请日：2008-04-18

申请人： Wenbin He ,  Wenfeng Li ,  Jun Zhai ,  Petter Ivmark ,  Gauri Tikekar

发明人： Wenbin He ,  Wenfeng Li ,  Jun Zhai ,  Petter Ivmark ,  Gauri Tikekar

IPC分类号： G06F17/30

CPC分类号： G06F17/30389

摘要： In accordance with one aspect of the invention, methods and apparatus for providing information for use in generating or modifying an expression are disclosed. Input from a user is received within an expression. A list of one or more suggestions is provided in response to the input. A selection of one of the suggestions in the list is received. The expression is then built to include the selection.

摘要翻译： 根据本发明的一个方面，公开了用于提供用于生成或修改表达式的信息的方法和装置。 在表达式中接收来自用户的输入。 响应于输入提供一个或多个建议的列表。 收到列表中的一个建议的选择。 然后构建表达式以包括选择。

公开(公告)号：US08008133B2

公开(公告)日：2011-08-30

申请号：US12029305

申请日：2008-02-11

申请人： Eric Tosaya ,  Jun Zhai ,  Chia-Ken Leong ,  Tom Ley

发明人： Eric Tosaya ,  Jun Zhai ,  Chia-Ken Leong ,  Tom Ley

IPC分类号： H01L21/00

CPC分类号： H01L23/16 ,  H01L23/04 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19105

摘要： Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

摘要翻译： 提供各种半导体芯片封装及其制造方法。 一方面，提供一种制造方法，其包括提供在第一侧上具有第一侧和第一多个无源器件的衬底。 加强框架连接在第一侧上。 加强框架具有第一和第二间隔开的相对的壁，其限定了第一多个无源器件定位在其中的通道，以及不覆盖衬底的第一侧的中心部分的中心开口。

公开(公告)号：US07679200B2

公开(公告)日：2010-03-16

申请号：US11853122

申请日：2007-09-11

申请人： Michael Z. Su ,  Jaime Bravo ,  Lei Fu ,  Jun Zhai

发明人： Michael Z. Su ,  Jaime Bravo ,  Lei Fu ,  Jun Zhai

IPC分类号： H01L23/48

CPC分类号： H01L23/585 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/00

摘要： Various semiconductor chip crack stops and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor substrate that has a first corner defined by a first edge and a second edge. A crack stop is formed in the semiconductor substrate. The crack stop includes a first projection extending to the first edge and a second projection extending to the second edge to fence off a portion of the semiconductor substrate that includes the first corner.

摘要翻译： 公开了各种半导体芯片裂纹停止及其制造方法。 在一个方面，提供一种制造方法，其包括提供具有由第一边缘和第二边缘限定的第一拐角的半导体基板。 在半导体衬底中形成裂纹停止。 裂纹挡板包括延伸到第一边缘的第一突起和延伸到第二边缘的第二突出部，以围绕包括第一拐角的半导体衬底的一部分。

公开(公告)号：US20090057928A1

公开(公告)日：2009-03-05

申请号：US11849545

申请日：2007-09-04

申请人： Jun Zhai ,  Ranjit Gannamani ,  Srinivasan Parthasarathy

发明人： Jun Zhai ,  Ranjit Gannamani ,  Srinivasan Parthasarathy

IPC分类号： H01L23/18 ,  H01L21/56

CPC分类号： H01L21/563 ,  H01L23/053 ,  H01L23/3164 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2924/00014

摘要： Various semiconductor chip underfills and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate to leave a gap therebetween, and forming an underfill layer in the gap. The underfill layer includes a first plurality of filler particles that have a first average size and a second plurality of filler particles that have a second average size smaller than the first average size such that the first plurality of filler particles is concentrated proximate the substrate and the second plurality of filler particles is concentrated proximate the semiconductor chip so that a bulk modulus of the underfill layer is larger proximate the substrate than proximate the semiconductor chip.

摘要翻译： 提供各种半导体芯片底层填料及其制造方法。 一方面，提供了一种制造方法，其包括将半导体芯片耦合到基板以在其间留下间隙，并在间隙中形成底部填充层。 底部填充层包括具有第一平均尺寸的第一多个填料颗粒和具有小于第一平均尺寸的第二平均尺寸的第二多个填料颗粒，使得第一多个填料颗粒在基材附近集中， 第二多个填料颗粒集中在半导体芯片附近，使得底部填充层的体积模量在靠近衬底的位置比靠近半导体芯片更大。

公开(公告)号：US20130058067A1

公开(公告)日：2013-03-07

申请号：US13227328

申请日：2011-09-07

申请人： Abraham F. YEE ,  Joe Greco ,  Jun Zhai ,  Joseph Minacapelli ,  John Y. Chen

发明人： Abraham F. YEE ,  Joe Greco ,  Jun Zhai ,  Joseph Minacapelli ,  John Y. Chen

IPC分类号： H05K7/00

CPC分类号： H01L23/36 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/00012

摘要： An IC system includes low-power chips, e.g., memory chips, located proximate one or more higher power chips, e.g., logic chips, without suffering the effects of overheating. The IC system may include a high-power chip disposed on a packaging substrate and a low-power chip embedded in the packaging substrate to form a stack. Because portions of the packaging substrate thermally insulate the low-power chip from the high-power chip, the low-power chip can be embedded in the IC system in close proximity to the high-power chip without being over heated by the high-power chip. Such close proximity between the low-power chip and the high-power chip advantageously shortens the path length of interconnects therebetween, which improves device performance and reduces interconnect parasitics in the IC system.

摘要翻译： IC系统包括位于一个或多个较高功率芯片（例如逻辑芯片）附近的低功率芯片，例如存储器芯片，而不会受到过热的影响。 IC系统可以包括设置在封装衬底上的大功率芯片和嵌入在封装衬底中的低功率芯片以形成堆叠。 由于包装基板的一部分将低功率芯片与大功率芯片隔热，所以低功率芯片可以嵌入到IC系统中，而不会被高功率芯片过度加热 芯片。 低功率芯片和高功率芯片之间的这种紧密接近有利地缩短了它们之间的互连的路径长度，这提高了器件性能并减少了IC系统中的互连寄生效应。

公开(公告)号：US07923850B2

公开(公告)日：2011-04-12

申请号：US12198227

申请日：2008-08-26

申请人： Mohammad Khan ,  Jun Zhai ,  Ranjit Gannamani ,  Raj N. Master

发明人： Mohammad Khan ,  Jun Zhai ,  Ranjit Gannamani ,  Raj N. Master

IPC分类号： H01L23/448 ,  H01L21/56

CPC分类号： H01L23/16 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

摘要： Various semiconductor chip arrangements and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip that has an external peripheral wall to a first side of a substrate. A first metallic ring is coupled to the first side of the substrate. The first metallic ring has an internal peripheral wall that frames the semiconductor chip and is separated from the external peripheral wall by a gap. The first metallic ring has a coefficient of thermal expansion less than about 6.0 10−6 K−1.

摘要翻译： 公开了各种半导体芯片布置及其制造方法。 一方面，提供一种制造方法，其包括将具有外周壁的半导体芯片与基板的第一侧耦合。 第一金属环耦合到衬底的第一侧。 第一金属环具有框架半导体芯片并且与外周壁隔开间隙的内周壁。 第一金属环的热膨胀系数小于约6.0×10 -6 K -1。

公开(公告)号：US07745264B2

公开(公告)日：2010-06-29

申请号：US11849545

申请日：2007-09-04

申请人： Jun Zhai ,  Ranjit Gannamani ,  Srinivasan Parthasarathy

发明人： Jun Zhai ,  Ranjit Gannamani ,  Srinivasan Parthasarathy

IPC分类号： H01L21/48 ,  H01L23/28

CPC分类号： H01L21/563 ,  H01L23/053 ,  H01L23/3164 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2924/00014

摘要： Various semiconductor chip underfills and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate to leave a gap therebetween, and forming an underfill layer in the gap. The underfill layer includes a first plurality of filler particles that have a first average size and a second plurality of filler particles that have a second average size smaller than the first average size such that the first plurality of filler particles is concentrated proximate the substrate and the second plurality of filler particles is concentrated proximate the semiconductor chip so that a bulk modulus of the underfill layer is larger proximate the substrate than proximate the semiconductor chip.

摘要翻译： 提供各种半导体芯片底层填料及其制造方法。 一方面，提供了一种制造方法，其包括将半导体芯片耦合到基板以在其间留下间隙，并在间隙中形成底部填充层。 底部填充层包括具有第一平均尺寸的第一多个填料颗粒和具有小于第一平均尺寸的第二平均尺寸的第二多个填料颗粒，使得第一多个填料颗粒在基材附近集中， 第二多个填料颗粒集中在半导体芯片附近，使得底部填充层的体积模量在靠近衬底的位置比靠近半导体芯片更大。