公开(公告)号：US08737028B2

公开(公告)日：2014-05-27

申请号：US13312047

申请日：2011-12-06

Applicant: James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra

Inventor： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra

IPC: H02H9/04 ,  G06F17/50

CPC classification number: H02H9/046

Abstract: Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.

Abstract translation: 用于响应电压轨上的静电放电（ESD）事件，ESD保护电路以及ESD保护电路的设计结构的方法。 ESD保护电路的RC网络包括耦合到节点处的场效应晶体管的电容器。 RC网络的节点与逆变器的输入端相连。 场效应晶体管与反相器的输出端相连。 响应于ESD事件，触发信号从RC网络提供给逆变器的输入，该驱动器驱动钳位装置以从ESD电压放电来自电压轨。 响应于ESD事件，RC网络的RC时间常数增加以维持钳位装置的电流放电。

公开(公告)号：US08692291B2

公开(公告)日：2014-04-08

申请号：US13431456

申请日：2012-03-27

Applicant: William F. Clark, Jr. ,  Robert J. Gauthier, Jr. ,  Junjun Li

Inventor： William F. Clark, Jr. ,  Robert J. Gauthier, Jr. ,  Junjun Li

IPC: H01L29/66

CPC classification number: H01L21/845 ,  H01L27/0262 ,  H01L27/1211

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract translation: 无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 形成器件结构，其包括器件区域中的第一导电类型的阱和阱中的第二导电性的掺杂区域。 器件区域由绝缘体上半导体衬底的器件层的一部分组成。 掺杂区域和阱的第一部分限定了结。 阱的第二部分位于器件区域的掺杂区域和外部侧壁之间。 可以对器件层的另一部分进行构图以形成翅片型场效应晶体管的鳍片。

公开(公告)号：US08637353B2

公开(公告)日：2014-01-28

申请号：US13013378

申请日：2011-01-25

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H01L21/82

CPC classification number: H01L22/30 ,  H01L21/76886 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/20 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  Y10T29/5313 ,  Y10T29/532 ,  H01L2924/00

Abstract: Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.

Abstract translation: 用于改变布线路径的电阻的方法和系统。 将布线路径的电阻与目标电阻值进行比较。 如果布线路径的电阻超过目标电阻值，则选择性地向布线路径施加电流，以物理地改变布线路径的一部分。 可以选择电流来改变布线路径，使得电阻下降到小于或等于目标电阻值的值。

公开(公告)号：US20130285211A1

公开(公告)日：2013-10-31

申请号：US13455732

申请日：2012-04-25

Applicant: Robert J. Gauthier, JR. ,  Jeffrey B. Johnson ,  Junjun Li

Inventor： Robert J. Gauthier, JR. ,  Jeffrey B. Johnson ,  Junjun Li

IPC: H01L29/00 ,  G06F17/50 ,  H01L21/20

CPC classification number: H01L27/1211 ,  G06F17/5068 ,  H01L21/3086 ,  H01L21/845

Abstract: Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.

Abstract translation: 鳍式场效应晶体管集成电路技术的器件结构，设计结构和制造方法。 构成器件结构的电极的第一和第二鳍片均由第一半导体材料构成。 第二翅片邻近第一翅片形成以限定分隔第一和第二翅片的间隙。 位于间隙中的是由第二半导体材料构成的层。

公开(公告)号：US08514535B2

公开(公告)日：2013-08-20

申请号：US12987276

申请日：2011-01-10

Applicant: Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra

Inventor： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra

IPC: H02H3/22

CPC classification number: H01L27/0285

Abstract: Structures and methods for electrostatic discharge (ESD) device control in an integrated circuit are provided. An ESD protection structure includes an input/output (I/O) pad, and an ESD field effect transistor (FET) including a drain connected to the I/O pad, a source connected to ground, and a gate. A first control FET includes a drain connected to the I/O pad, a source connected to the gate of the ESD FET, and a gate connected to ground. A second control FET includes a drain connected to the gate of the ESD FET and the source of the first control FET, a source connected to ground, and a gate connected to the I/O pad.

Abstract translation: 提供集成电路中静电放电（ESD）器件控制的结构和方法。 ESD保护结构包括输入/​​输出（I / O）焊盘和包括连接到I / O焊盘的漏极，连接到地的源极和栅极的ESD场效应晶体管（FET）。 第一控制FET包括连接到I / O焊盘的漏极，连接到ESD FET的栅极的源极和连接到地的栅极。 第二控制FET包括连接到ESD FET的栅极和第一控制FET的源极的漏极，连接到地的源极和连接到I / O焊盘的栅极。

公开(公告)号：US08503140B2

公开(公告)日：2013-08-06

申请号：US12898013

申请日：2010-10-05

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H02H9/00

CPC classification number: H01L27/0262 ,  H01L29/747 ,  H01L29/87 ,  H02H9/04

Abstract: Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode of a first of the back-to-back stacked SCR is connected to an input. An anode of a second of the back-to-back stacked SCR is connected to ground. Cathodes of the first and second of the back-to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively and deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.

Abstract translation: 提供用于高压针ESD保护的双向背对背堆叠SCR，制造方法和设计结构。 该器件包括对称双向背对背层叠可控硅整流器（SCR）。 背对背堆叠的SCR中的第一个的阳极连接到输入。 背对背堆叠的SCR的第二个的阳极连接到地面。 第一个和第二个背靠背堆叠的SCR的阴极连接在一起。 对称双向背靠背SCR中的每一个包括一对二极管，其引导电流朝向阴极，其在施加电压时有效地变得有效地反向偏置，并且从对称的双向后向SCR中的一个去激活元件， 另一个对称双向背对背SCR的二极管在与反向偏置二极管相同的方向上直流电流，反向SCR。

公开(公告)号：US20130020645A1

公开(公告)日：2013-01-24

申请号：US13188094

申请日：2011-07-21

Applicant: John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Rahul Mishra ,  Junjun Li ,  Mujahid Muhammad

Inventor： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Rahul Mishra ,  Junjun Li ,  Mujahid Muhammad

IPC: H01L29/772 ,  G06F9/45 ,  H01L21/336

CPC classification number: H01L29/41775 ,  H01L27/0266 ,  H01L29/1087 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.

Abstract translation: 静电放电保护装置，静电放电保护装置的制造方法以及静电放电保护装置的设计结构。 第一场效应晶体管的漏极和较高电阻的扩散电阻可以形成为掺杂区域的不同部分。 可以使用布置在掺杂区域中的介电材料的隔离区域和选择性硅化物形成来限定与第一场效应晶体管的漏极直接耦合的扩散电阻器。 静电放电保护器件还可以包括第二场效应晶体管，其具有作为与扩散电阻器直接耦合并且由扩散电阻器与第一场效应晶体管的漏极间接耦合的掺杂区域的一部分的漏极。

公开(公告)号：US08354722B2

公开(公告)日：2013-01-15

申请号：US13149174

申请日：2011-05-31

Applicant: John B. Campi, Jr. ,  Shunhua Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

Inventor： John B. Campi, Jr. ,  Shunhua Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

IPC: H01L29/78 ,  H01L29/788 ,  H02H9/00

CPC classification number: H01L29/742 ,  H01L27/0262

Abstract: An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.

Abstract translation: 静电放电（ESD）保护电路，制造ESD保护电路的方法，提供ESD保护的方法以及ESD保护电路的设计结构。 可以在p阱中形成NFET，并且可以在n阱中形成PFET。 在p阱和n阱之间形成的对接p-n结导致形成与NFET和PFET集成的SCR的NPNP结构。 NFET，PFET和SCR被配置为共同保护诸如电源板的焊盘免受ESD事件的影响。 在正常工作期间，NFET，PFET和SCR被RC触发电路偏置，使得ESD保护电路处于高阻抗状态。 在芯片无电源时的ESD事件期间，RC触发电路输出触发信号，使SCR，NFET和PFET进入导通状态，并协同地将ESD电流从受保护的焊盘分流。

公开(公告)号：US20120305984A1

公开(公告)日：2012-12-06

申请号：US13149174

申请日：2011-05-31

Applicant: John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

Inventor： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

IPC: H01L29/747 ,  G06F17/50 ,  H01L21/332

CPC classification number: H01L29/742 ,  H01L27/0262

Abstract: An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.

Abstract translation: 静电放电（ESD）保护电路，制造ESD保护电路的方法，提供ESD保护的方法以及ESD保护电路的设计结构。 可以在p阱中形成NFET，并且可以在n阱中形成PFET。 在p阱和n阱之间形成的对接p-n结导致形成与NFET和PFET集成的SCR的NPNP结构。 NFET，PFET和SCR被配置为共同保护诸如电源板的焊盘免受ESD事件的影响。 在正常工作期间，NFET，PFET和SCR被RC触发电路偏置，使得ESD保护电路处于高阻抗状态。 在芯片无电源时的ESD事件期间，RC触发电路输出触发信号，使SCR，NFET和PFET进入导通状态，并协同地将ESD电流从受保护的焊盘分流。

公开(公告)号：US20120187525A1

公开(公告)日：2012-07-26

申请号：US13012137

申请日：2011-01-24

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H01L29/12 ,  G06F17/50 ,  H01L21/36

CPC classification number: H01L27/0255 ,  G06F17/5022 ,  G06F17/5045 ,  H01L27/0262 ,  H01L27/1203 ,  H01L29/6609 ,  H01L29/66393 ,  H01L29/7436 ,  H01L29/861

Abstract: Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.

Abstract translation: 在SOI工艺中具有减小的结面积的器件结构，制造器件结构的方法以及横向二极管的设计结构。 器件结构包括位于器件区域中并与阳极和阴极之间的p-n结相交的一个或多个电介质区域，例如STI区域。 可以使用浅沟槽隔离技术形成的电介质区域用于在p-n结和阳极侧向间隔的位置处减小p-n结相对于阴极宽度区域的宽度。 介质区域的宽度差和存在产生不对称二极管结构。 由电介质区域占据的器件区域的体积被最小化以保持阴极和阳极的体积。