公开(公告)号：US07809094B2

公开(公告)日：2010-10-05

申请号：US11872667

申请日：2007-10-15

Applicant: Junyi Xu ,  Binfan Liu ,  Vladimir Radionov ,  Weimin Zhang

Inventor： Junyi Xu ,  Binfan Liu ,  Vladimir Radionov ,  Weimin Zhang

IPC: H03D1/04

CPC classification number: H04B1/0475

Abstract: A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal.

Abstract translation: 用于消除或衰减谐波噪声而不使输入信号失真的装置和方法。 示例性装置包括使用估计环路来产生人造信号以消除或衰减谐波的影响。 估计环路包括适于通过处理或组合输入信号和人造信号来产生混合信号的混频器。 估计回路包括误差检测器，低通滤波器，参数估计器和数控振荡器。 参数估计器产生与输入谐波支路的相位，频率和幅度相关的信息，并由数控振荡器用于产生人为信号。 如果混合信号包含较低水平的谐波残差，则在输出端产生混合信号来代替输入信号。

公开(公告)号：US08352834B2

公开(公告)日：2013-01-08

申请号：US12652167

申请日：2010-01-05

Applicant: Binfan Liu ,  Junyi Xu

Inventor： Binfan Liu ,  Junyi Xu

IPC: G06F11/00 ,  H03M13/00 ,  H04L1/18 ,  G11C29/00

CPC classification number: G11C7/1072 ,  H03M13/2707 ,  H03M13/2721 ,  H03M13/2732 ,  H03M13/2906 ,  H03M13/2936

Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

Abstract translation: 提供了使用外部DDR SDRAM执行高速多通道前向纠错的系统和方法。 根据一个示例性方面，交织器/解交织器通过隐藏有效和预充电周期来对通过突发定向的DDR SDRAM执行读和写访问，以实现高数据速率操作。 交织器/解交织器将DDR SDRAM中的数据作为读取块和写入块访问。 每个块包括两个数据序列。 每个数据序列还包括要交织/解交织的预定数量的数据字。 当处理前面的数据序列时，会发出一个数据序列的PRECHARGE和ACTIVE命令。 一个读/写数据序列中的数据在DDR SDRAM的同一组内具有相同的行地址。

公开(公告)号：US20110113305A1

公开(公告)日：2011-05-12

申请号：US12652167

申请日：2010-01-05

Applicant: Binfan Liu ,  Junyi Xu

Inventor： Binfan Liu ,  Junyi Xu

IPC: H03M13/05 ,  G06F12/02 ,  G06F12/06 ,  G06F11/10

CPC classification number: G11C7/1072 ,  H03M13/2707 ,  H03M13/2721 ,  H03M13/2732 ,  H03M13/2906 ,  H03M13/2936

Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

Abstract translation: 提供了使用外部DDR SDRAM执行高速多通道前向纠错的系统和方法。 根据一个示例性方面，交织器/解交织器通过隐藏有效和预充电周期来对通过突发定向的DDR SDRAM执行读和写访问，以实现高数据速率操作。 交织器/解交织器将DDR SDRAM中的数据作为读取块和写入块访问。 每个块包括两个数据序列。 每个数据序列还包括要交织/解交织的预定数量的数据字。 当处理前面的数据序列时，会发出一个数据序列的PRECHARGE和ACTIVE命令。 一个读/写数据序列中的数据在DDR SDRAM的同一组内具有相同的行地址。

公开(公告)号：US08401092B1

公开(公告)日：2013-03-19

申请号：US12848073

申请日：2010-07-30

Applicant: Binfan Liu ,  Junyi Xu ,  Weimin Zhang

Inventor： Binfan Liu ,  Junyi Xu ,  Weimin Zhang

IPC: H04B3/00

CPC classification number: H04L7/0037 ,  H03L7/06 ,  H04J3/0638 ,  H04J3/0658 ,  H04L27/36

Abstract: Efficient synchronization techniques that support multiple reference clocks in an EQAM device. Consider a plurality of different modulators in the EQAM device receiving data from a corresponding plurality of different sources having corresponding different timing references (i.e., different source reference clocks). To accommodate this, the modulators all operate using a common system clock, and each modulator is provided with a phase synchronizer. The phase synchronizer synchronizes the modulated symbol phases to the corresponding reference clock.

Abstract translation: 在EQAM设备中支持多个参考时钟的高效同步技术。 考虑在EQAM设备中接收来自具有对应的不同定时参考（即，不同的源参考时钟）的相应多个不同源的数据的多个不同调制器。 为了适应这一点，调制器都使用公共系统时钟进行操作，并且每个调制器都配备有相位同步器。 相位同步器将调制的符号相位同步到相应的参考时钟。

公开(公告)号：US20090096514A1

公开(公告)日：2009-04-16

申请号：US11872667

申请日：2007-10-15

Applicant: Junyi Xu ,  Binfan Liu ,  Vladimir Radionov ,  Weimin Zhang

Inventor： Junyi Xu ,  Binfan Liu ,  Vladimir Radionov ,  Weimin Zhang

IPC: H04B1/10

CPC classification number: H04B1/0475

Abstract: A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal.

Abstract translation: 用于消除或衰减谐波噪声而不使输入信号失真的装置和方法。 示例性装置包括使用估计环路来产生人造信号以消除或衰减谐波的影响。 估计环路包括适于通过处理或组合输入信号和人造信号来产生混合信号的混频器。 估计回路包括误差检测器，低通滤波器，参数估计器和数控振荡器。 参数估计器产生与输入谐波支路的相位，频率和幅度相关的信息，并由数控振荡器用于产生人为信号。 如果混合信号包含较低水平的谐波残差，则在输出端产生混合信号来代替输入信号。