公开(公告)号：US20250069670A1

公开(公告)日：2025-02-27

申请号：US18946968

申请日：2024-11-14

Applicant: Kioxia Corporation

Inventor： Kosuke YANAGIDAIRA ,  Hiroshi TSUBOUCHI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/32 ,  H10B43/10 ,  H10B43/27

Abstract: A memory system includes a semiconductor memory device and a memory controller configured to send a command to the device. The device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a sequencer. The sequencer, in response to the command, reads data stored by the memory cell by applying a first voltage to the first transistor and a second voltage to the source line during a first time period, applying a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applying the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.

公开(公告)号：US12238936B2

公开(公告)日：2025-02-25

申请号：US17684736

申请日：2022-03-02

Applicant: Kioxia Corporation

Inventor： Yuichi Ito ,  Taichi Igarashi

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: According to one embodiment, a memory device includes: a switching element including first and second conductive layers, and a variable resistive layer between the first and second conductive layers. The first or second conductive layers includes a first layer, a second layer between the first layer and the variable resistive layer, and a third layer between the first layer and the second layer. Each of the first and second layers is selected from a layer including carbon, a layer including nitrogen and carbon, a layer including nitrogen and titanium, a layer including nitrogen and tantalum, a layer including tungsten, a layer including nitrogen and tungsten, and a layer including platinum. The third layer includes at least one selected from lithium, sodium, magnesium, calcium, titanium, or lanthanum.

公开(公告)号：US12236139B2

公开(公告)日：2025-02-25

申请号：US18331804

申请日：2023-06-08

Applicant: Kioxia Corporation

Inventor： Akio Sugahara ,  Masahiro Yoshihara

IPC: G06F3/06 ,  G06F12/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.

公开(公告)号：US12235771B2

公开(公告)日：2025-02-25

申请号：US18174745

申请日：2023-02-27

Applicant: Kioxia Corporation

Inventor： Shuichi Watanabe

IPC: G06F12/10

Abstract: According to one embodiment, in response to receiving a read command from a host, a controller executes a command process of reading data from a nonvolatile memory. The controller executes an address translation process of translating a virtual address specified in the read command to a physical address for accessing a memory of the host. In the address translation process, the controller transmits an address translation request to the host. In response to receiving from the host a response indicating that obtainment of address translation information fails, the controller suspends the command process until the address translation information is obtained, and after the address translation information is obtained, resumes the command process.

公开(公告)号：US12229450B2

公开(公告)日：2025-02-18

申请号：US18524477

申请日：2023-11-30

Applicant: KIOXIA CORPORATION

Inventor： Akio Sugahara ,  Zhao Lu ,  Takehisa Kurosawa ,  Yuji Nagai

IPC: G11C7/00 ,  G06F3/06 ,  G11C16/04 ,  G11C16/26

Abstract: A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.

公开(公告)号：US12229443B2

公开(公告)日：2025-02-18

申请号：US17806841

申请日：2022-06-14

Applicant: Kioxia Corporation

Inventor： Toshiro Nagasaka

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a storage area, and a controller. The controller acquires a request from a submission queue included in a host, generates one or more commands to be executed by the nonvolatile memory in accordance with the request, and stores the commands to the storage area. The controller controls throttling of acquisition of requests from the submission queue in accordance with the number of commands in the storage area and the number of requests in the submission queue.

公开(公告)号：US20250055702A1

公开(公告)日：2025-02-13

申请号：US18795461

申请日：2024-08-06

Applicant: Kioxia Corporation

Inventor： Masahiro KUSAKA

IPC: H04L9/32 ,  H04L9/14

Abstract: A memory system includes a first storage; a second storage storing log information indicating a history of accesses to the first storage; a third storage storing a first private key and a first public key; and a processor configured to convert the log information into a first hash value by inputting the log information into a hash function, sign the first hash value using the first private key, and generate a first signature. The processor is further configured to convert the log information read from the second storage into a second hash value by inputting the log information into the hash function; and perform signature verification using the first public key paired with the first private key and the second hash value.

公开(公告)号：US20250054553A1

公开(公告)日：2025-02-13

申请号：US18930319

申请日：2024-10-29

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA ,  Shohei ASAMI ,  Masamichi FUJIWARA

IPC: G11C16/26 ,  G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.

公开(公告)号：US20250054521A1

公开(公告)日：2025-02-13

申请号：US18928444

申请日：2024-10-28

Applicant: KIOXIA CORPORATION

Inventor： Masato SUGITA ,  Naoki KIMURA ,  Daisuke KIMURA

IPC: G11C5/04 ,  G06F13/42 ,  G06F16/9535 ,  G11C5/02 ,  G11C5/06 ,  G11C14/00 ,  G11C16/04

Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

公开(公告)号：US12224020B2

公开(公告)日：2025-02-11

申请号：US17902754

申请日：2022-09-02

Applicant: Kioxia Corporation

Inventor： Kenro Kikuchi ,  Masahiko Iga ,  Nobushi Matsuura

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34

Abstract: A semiconductor storage device of embodiments includes a block constituted with a plurality of strings each including a plurality of memory cell transistors, a plurality of word lines, a bit line, a source line, and a control circuit configured to perform erase operation on the plurality of memory cell transistors, and the control circuit changes setting of first erase-verify operation included in the erase operation for an open block including a memory cell transistor having an erase level and setting of second erase-verify operation included in erase operation for a closed block not including a memory cell transistor having an erase block.