公开(公告)号：US08625354B2

公开(公告)日：2014-01-07

申请号：US12982558

申请日：2010-12-30

申请人： Ka Young Cho ,  Young Soo Park

发明人： Ka Young Cho ,  Young Soo Park

IPC分类号： G11C16/10

CPC分类号： G11C16/3459 ,  G11C16/3454

摘要： A semiconductor memory device includes a voltage generator configured to supply a program voltage, a sub-verification voltage, or a target verification voltage to memory cells selected during a program operation, page buffers configured to latch first data according to results from comparing threshold voltages of the selected memory cells with the sub-verification voltage and latch second data according to results from comparing the threshold voltages of the memory cells with the target verification voltage, a sub-pass check circuit configured to output a sub-pass signal in response to the first data outputted from the page buffers, a main pass check circuit configured to output a main pass signal in response to the second data outputted from the page buffers, and a control circuit configured to control whether the voltage generator supplies the sub-verification voltage and the target verification voltage in response to the sub-pass signal and the main pass signal.

摘要翻译： 半导体存储器件包括：电压发生器，被配置为将程序电压，子验证电压或目标验证电压提供给在编程操作期间选择的存储器单元，所述页缓冲器被配置为根据比较阈值电压的结果来锁存第一数据 根据将存储单元的阈值电压与目标验证电压进行比较的结果，将所选择的具有子验证电压的存储单元和锁存第二数据进行锁存;副通路检查电路，被配置为响应于所述目标验证电压输出子通过信号 从页缓冲器输出的第一数据，主通检查电路，配置为响应于从页缓冲器输出的第二数据输出主通道信号;以及控制电路，被配置为控制电压发生器是否提供子验证电压，以及 响应于副通信号和主通道信号的目标验证电压。

公开(公告)号：US20110158000A1

公开(公告)日：2011-06-30

申请号：US12982558

申请日：2010-12-30

申请人： Ka Young CHO ,  Young Soo Park

发明人： Ka Young CHO ,  Young Soo Park

IPC分类号： G11C16/10

CPC分类号： G11C16/3459 ,  G11C16/3454

摘要： A semiconductor memory device includes a voltage generator configured to supply a program voltage, a sub-verification voltage, or a target verification voltage to memory cells selected during a program operation, page buffers configured to latch first data according to results from comparing threshold voltages of the selected memory cells with the sub-verification voltage and latch second data according to results from comparing the threshold voltages of the memory cells with the target verification voltage, a sub-pass check circuit configured to output a sub-pass signal in response to the first data outputted from the page buffers, a main pass check circuit configured to output a main pass signal in response to the second data outputted from the page buffers, and a control circuit configured to control whether the voltage generator supplies the sub-verification voltage and the target verification voltage in response to the sub-pass signal and the main pass signal.

摘要翻译： 半导体存储器件包括：电压发生器，被配置为将程序电压，子验证电压或目标验证电压提供给在编程操作期间选择的存储器单元，所述页缓冲器被配置为根据比较阈值电压的结果来锁存第一数据 根据将存储单元的阈值电压与目标验证电压进行比较的结果，将所选择的具有子验证电压的存储单元和锁存第二数据进行锁存;副通路检查电路，被配置为响应于所述目标验证电压输出子通过信号 从页缓冲器输出的第一数据，主通检查电路，配置为响应于从页缓冲器输出的第二数据输出主通道信号;以及控制电路，被配置为控制电压发生器是否提供子验证电压，以及 响应于副通信号和主通道信号的目标验证电压。