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    Semiconductor memory device, memory system having semiconductor memory device, and method for testing memory system
    1.
    发明授权
    Semiconductor memory device, memory system having semiconductor memory device, and method for testing memory system 有权
    半导体存储器件，具有半导体存储器件的存储器系统和用于测试存储器系统的方法

    公开(公告)号：US07634697B2

    公开(公告)日：2009-12-15

    申请号：US11853107

    申请日：2007-09-11

    申请人： Kae-Won Ha ,  Dong-Jun Kim ,  Jin-Soo Park ,  Keun-Soo Jo

    发明人： Kae-Won Ha ,  Dong-Jun Kim ,  Jin-Soo Park ,  Keun-Soo Jo

    IPC分类号： G11C29/00

    CPC分类号： G11C7/1045 ,  G11C7/1051 ,  G11C7/1063 ,  G11C29/02 ,  G11C29/022

    摘要： Embodiments of the invention include features in the semiconductor memory device that are configured to receive command signals from a memory controller and selectively output at least a portion of the received command signals back to the memory controller for verification. Embodiments of the invention also provide methods for verifying the proper communication of command signals from a memory controller to a semiconductor memory device. Embodiments of the invention also provide systems and methods for testing memory cells in a semiconductor memory device.

    摘要翻译： 本发明的实施例包括半导体存储器件中的特征，其被配置为从存储器控制器接收命令信号并且有选择地将接收到的命令信号的至少一部分输出回存储器控制器进行验证。 本发明的实施例还提供了用于验证从存储器控制器到半导体存储器件的命令信号的正确通信的方法。 本发明的实施例还提供了用于测试半导体存储器件中的存储单元的系统和方法。

    MEMORY DEVICE CAPABLE OF OPERATION IN WIDE TEMPERATURE RANGE AND DATA PROCESSING SYSTEM AND METHOD OF OPERATING THE SAME
    3.
    发明申请
    MEMORY DEVICE CAPABLE OF OPERATION IN WIDE TEMPERATURE RANGE AND DATA PROCESSING SYSTEM AND METHOD OF OPERATING THE SAME 有权
    能够在宽温度范围和数据处理系统中操作的存储器件及其操作方法

    公开(公告)号：US20160078907A1

    公开(公告)日：2016-03-17

    申请号：US14801860

    申请日：2015-07-17

    申请人： Mi Young WOO ,  Kae Won HA ,  Myong Jae KIM

    发明人： Mi Young WOO ,  Kae Won HA ,  Myong Jae KIM

    IPC分类号： G11C7/04 ,  G06F3/06 ,  G11C11/406

    CPC分类号： G11C7/04 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G11C11/40626

    摘要： A data processing system includes a first memory, a second memory, a temperature sensor, and a controller. The temperature sensor is configured to sense a temperature at the data processing system and generate a temperature signal. The controller is configured to control whether the first memory is enabled or disabled and whether the second memory is enabled or disabled based on the temperature signal and based on a first temperature threshold associated with the first memory and a second temperature threshold associated with the second memory.

    摘要翻译： 数据处理系统包括第一存储器，第二存储器，温度传感器和控制器。 温度传感器被配置为感测数据处理系统的温度并产生温度信号。 控制器被配置为基于温度信号并且基于与第一存储器相关联的第一温度阈值和与第二存储器相关联的第二温度阈值来控制第一存储器是启用还是禁用，以及是否启用或禁用第二存储器 。

    SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM HAVING SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR TESTING MEMORY SYSTEM
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM HAVING SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR TESTING MEMORY SYSTEM 有权
    半导体存储器件，具有半导体存储器件的存储器系统以及用于测试存储器系统的方法

    公开(公告)号：US20080080268A1

    公开(公告)日：2008-04-03

    申请号：US11853107

    申请日：2007-09-11

    申请人： Kae-Won HA ,  Dong-Jun KIM ,  Jin-Soo PARK ,  Keun-Soo JO

    发明人： Kae-Won HA ,  Dong-Jun KIM ,  Jin-Soo PARK ,  Keun-Soo JO

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1045 ,  G11C7/1051 ,  G11C7/1063 ,  G11C29/02 ,  G11C29/022

    摘要： Embodiments of the invention include features in the semiconductor memory device that are configured to receive command signals from a memory controller and selectively output at least a portion of the received command signals back to the memory controller for verification. Embodiments of the invention also provide methods for verifying the proper communication of command signals from a memory controller to a semiconductor memory device. Embodiments of the invention also provide systems and methods for testing memory cells in a semiconductor memory device.

    摘要翻译： 本发明的实施例包括半导体存储器件中的特征，其被配置为从存储器控制器接收命令信号并且有选择地将接收到的命令信号的至少一部分输出回存储器控制器进行验证。 本发明的实施例还提供了用于验证从存储器控制器到半导体存储器件的命令信号的正确通信的方法。 本发明的实施例还提供了用于测试半导体存储器件中的存储单元的系统和方法。

    Memory module with parallel testing
    5.
    发明授权
    Memory module with parallel testing 失效
    内存模块并行测试

    公开(公告)号：US07246280B2

    公开(公告)日：2007-07-17

    申请号：US11086059

    申请日：2005-03-22

    申请人： Youn-Cheul Kim ,  Hee-Joo Choi ,  Kae-Won Ha ,  Joon-Hee Lee

    发明人： Youn-Cheul Kim ,  Hee-Joo Choi ,  Kae-Won Ha ,  Joon-Hee Lee

    IPC分类号： G11C29/00

    CPC分类号： G11C29/40 ,  G11C29/28 ,  G11C2029/2602

    摘要： Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.

    摘要翻译： 存储器模块的每个存储器芯片测试来自X个存储器块的总共N个数据位用于有效测试，并从其中一个存储器块输出N / X个测试数据位。 存储器模块包括多个存储器芯片和多个比较单元。 每个比较单元设置在相应的存储器芯片内，用于从多个存储器块测试多个测试数据位。 此外，每个比较单元从相应的存储器芯片内的一个存储器块输出测试数据位。

    Memory device and memory control unit
    7.
    发明授权
    Memory device and memory control unit 有权
    存储器和存储器控制单元

    公开(公告)号：US08812928B2

    公开(公告)日：2014-08-19

    申请号：US13368352

    申请日：2012-02-08

    申请人： Kae-Won Ha

    发明人： Kae-Won Ha

    IPC分类号： H03M13/00 ,  H03M13/09 ,  H03M13/11 ,  G06F11/10

    CPC分类号： H03M13/09 ,  G06F11/1004 ,  H03M13/11

    摘要： A memory device is configured to generate a signal having a temperature compensation function. The device includes a mode register configured to store error detection and correction (EDC) mode data, and an EDC pattern generator configured to receive pattern information and period information included in the mode data and to generate an EDC pattern signal based on the pattern information and the period information. The EDC pattern signal is a periodic signal obtained by repeating a signal pattern based on the pattern information at a periodic rate corresponding to a signal period based on the period information. In some cases, the EDC pattern signal may be disabled during a portion of the signal period.

    摘要翻译： 存储器件被配置为产生具有温度补偿功能的信号。 该装置包括配置为存储错误检测和校正（EDC）模式数据的模式寄存器和被配置为接收包括在模式数据中的模式信息和周期信息并且基于模式信息生成EDC模式信号的EDC模式发生器， 期间信息。 EDC模式信号是通过基于周期信息以对应于信号周期的周期速率基于模式信息重复信号模式而获得的周期信号。 在某些情况下，EDC模式信号可能在信号周期的一部分期间被禁用。

    MEMORY DEVICE AND MEMORY CONTROL UNIT
    9.
    发明申请
    MEMORY DEVICE AND MEMORY CONTROL UNIT 有权
    存储器件和存储器控制单元

    公开(公告)号：US20120216095A1

    公开(公告)日：2012-08-23

    申请号：US13368352

    申请日：2012-02-08

    申请人： Kae-won HA

    发明人： Kae-won HA

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/09 ,  G06F11/1004 ,  H03M13/11

    摘要： A memory device is configured to generate a signal having a temperature compensation function. The device includes a mode register configured to store error detection and correction (EDC) mode data, and an EDC pattern generator configured to receive pattern information and period information included in the mode data and to generate an EDC pattern signal based on the pattern information and the period information. The EDC pattern signal is a periodic signal obtained by repeating a signal pattern based on the pattern information at a periodic rate corresponding to a signal period based on the period information. In some cases, the EDC pattern signal may be disabled during a portion of the signal period.

    摘要翻译： 存储器件被配置为产生具有温度补偿功能的信号。 该装置包括配置为存储错误检测和校正（EDC）模式数据的模式寄存器和被配置为接收包括在模式数据中的模式信息和周期信息并且基于模式信息生成EDC模式信号的EDC模式发生器， 期间信息。 EDC模式信号是通过基于周期信息以对应于信号周期的周期速率基于模式信息重复信号模式而获得的周期信号。 在某些情况下，EDC模式信号可能在信号周期的一部分期间被禁用。

    Memory module with parallel testing
    10.
    发明申请
    Memory module with parallel testing 失效
    内存模块并行测试

    公开(公告)号：US20080005631A1

    公开(公告)日：2008-01-03

    申请号：US11811551

    申请日：2007-06-11

    申请人： Youn-Cheul Kim ,  Hee-Joo Choi ,  Kae-Won Ha ,  Joon-Hee Lee

    发明人： Youn-Cheul Kim ,  Hee-Joo Choi ,  Kae-Won Ha ,  Joon-Hee Lee

    IPC分类号： G11C29/08

    CPC分类号： G11C29/40 ,  G11C29/28 ,  G11C2029/2602

    摘要： Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.

    摘要翻译： 存储器模块的每个存储器芯片测试来自X个存储器块的总共N个数据位用于有效测试，并从其中一个存储器块输出N / X数据位。 存储器模块包括多个存储器芯片和多个比较单元。 每个比较单元设置在相应的存储器芯片内，用于从多个存储器块测试多个数据位。 此外，每个比较单元从相应的存储器芯片内的一个存储块输出数据位。