公开(公告)号：US20100144117A1

公开(公告)日：2010-06-10

申请号：US12708519

申请日：2010-02-18

申请人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

发明人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

IPC分类号： H01L21/762

CPC分类号： H01L29/045 ,  H01L21/76232 ,  H01L29/7846

摘要： A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.

摘要翻译： 沟槽形成在半导体衬底的表面层中，沟槽围绕有源区。 在半导体器件上沉积由绝缘材料制成的下绝缘膜，下绝缘膜填充沟槽的下部区域并在上部区域留下空的空间。 在其上具有拉伸应力的由绝缘材料制成的上绝缘膜沉积在下绝缘膜上，上绝缘膜填充留在上部空间中的空白空间。 去除沉积在半导体衬底上而不是在沟槽中的上绝缘膜和下绝缘膜。

公开(公告)号：US20050287756A1

公开(公告)日：2005-12-29

申请号：US10950451

申请日：2004-09-28

申请人： Kaina Suzuki ,  Shigeo Satoh

发明人： Kaina Suzuki ,  Shigeo Satoh

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L27/01 ,  H01L27/06 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/76229 ,  H01L27/0629 ,  H01L28/20

摘要： A first well is formed in the surface layer of a semiconductor substrate, the first layer being of a first conductivity type, the first well being of a second conductivity type opposite to the first conductivity type. A pair of current input/output ports are connected to the first well, the pair of current input/output ports being used for flowing current through the first well along the direction parallel to a substrate surface. A second well of the first conductivity type is disposed between the pair of current input/output ports, the second well being shallower than the first well. A resistor element is provided which facilitates to have a desired resistance value.

摘要翻译： 第一阱形成在半导体衬底的表面层中，第一层是第一导电型，第一阱是与第一导电类型相反的第二导电类型。 一对当前输入/输出端口连接到第一阱，该对电流输入/输出端口用于沿着平行于衬底表面的方向流过第一阱的电流。 第一导电类型的第二阱设置在一对电流输入/输出端口之间，第二阱比第一阱浅。 提供了一种有助于具有所需电阻值的电阻元件。

公开(公告)号：US20120038004A1

公开(公告)日：2012-02-16

申请号：US13089743

申请日：2011-04-19

申请人： Shigeo Satoh ,  Kaina Suzuki

发明人： Shigeo Satoh ,  Kaina Suzuki

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/7846 ,  H01L21/76232 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/7843

摘要： A first insulating film is formed above a semiconductor substrate with a device isolation insulating film defining a device region, a gate electrode and source/drain region formed. The first insulating film is etched, leaving the first insulating film in a recess formed in an edge of the device isolation insulating film. A second insulating film applying a stress to the semiconductor substrate is formed after etching the first insulating film.

摘要翻译： 在半导体衬底之上形成第一绝缘膜，其中器件隔离绝缘膜限定形成器件区域，栅极电极和源极/漏极区域。 蚀刻第一绝缘膜，将第一绝缘膜留在形成在器件隔离绝缘膜的边缘中的凹槽中。 在蚀刻第一绝缘膜之后形成向半导体衬底施加应力的第二绝缘膜。

公开(公告)号：US20070228488A1

公开(公告)日：2007-10-04

申请号：US11541782

申请日：2006-10-03

申请人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

发明人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

IPC分类号： H01L29/76

CPC分类号： H01L29/045 ,  H01L21/76232 ,  H01L29/7846

摘要： A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film has therein a stress generating tensile strain in a surface layer of the active region.

摘要翻译： 在半导体衬底的表面层中形成有围绕有源区的沟槽。 由绝缘材料制成的下绝缘膜填充沟槽的下部区域。 上绝缘膜填充下绝缘膜上方的沟槽的区域。 上部绝缘膜在其中具有在有源区的表面层中的应力产生拉伸应变。

公开(公告)号：US07557429B2

公开(公告)日：2009-07-07

申请号：US10950451

申请日：2004-09-28

申请人： Kaina Suzuki ,  Shigeo Satoh

发明人： Kaina Suzuki ,  Shigeo Satoh

IPC分类号： H01L23/58

CPC分类号： H01L21/76229 ,  H01L27/0629 ,  H01L28/20

摘要： A first well is formed in the surface layer of a semiconductor substrate, the first layer being of a first conductivity type, the first well being of a second conductivity type opposite to the first conductivity type. A pair of current input/output ports are connected to the first well, the pair of current input/output ports being used for flowing current through the first well along the direction parallel to a substrate surface. A second well of the first conductivity type is disposed between the pair of current input/output ports, the second well being shallower than the first well. A resistor element is provided which facilitates to have a desired resistance value.

摘要翻译： 第一阱形成在半导体衬底的表面层中，第一层是第一导电型，第一阱是与第一导电类型相反的第二导电类型。 一对当前输入/输出端口连接到第一阱，该对电流输入/输出端口用于沿着平行于衬底表面的方向流过第一阱的电流。 第一导电类型的第二阱设置在一对电流输入/输出端口之间，第二阱比第一阱浅。 提供了一种有助于具有所需电阻值的电阻元件。

公开(公告)号：US20060281245A1

公开(公告)日：2006-12-14

申请号：US11358317

申请日：2006-02-22

申请人： Masaki Okuno ,  Sadahiro Kishii ,  Hiroshi Morioka ,  Masanori Terahara ,  Shigeo Satoh ,  Kaina Suzuki

发明人： Masaki Okuno ,  Sadahiro Kishii ,  Hiroshi Morioka ,  Masanori Terahara ,  Shigeo Satoh ,  Kaina Suzuki

IPC分类号： H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/76235 ,  H01L21/823878

摘要： A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.

公开(公告)号：US08691654B2

公开(公告)日：2014-04-08

申请号：US13089743

申请日：2011-04-19

申请人： Shigeo Satoh ,  Kaina Suzuki

发明人： Shigeo Satoh ,  Kaina Suzuki

IPC分类号： H01L21/336

CPC分类号： H01L29/7846 ,  H01L21/76232 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/7843

摘要： A first insulating film is formed above a semiconductor substrate with a device isolation insulating film defining a device region, a gate electrode and source/drain region formed. The first insulating film is etched, leaving the first insulating film in a recess formed in an edge of the device isolation insulating film. A second insulating film applying a stress to the semiconductor substrate is formed after etching the first insulating film.

摘要翻译： 在半导体衬底之上形成第一绝缘膜，其中器件隔离绝缘膜限定形成器件区域，栅极电极和源极/漏极区域。 蚀刻第一绝缘膜，将第一绝缘膜留在形成在器件隔离绝缘膜的边缘中的凹槽中。 在蚀刻第一绝缘膜之后，形成向半导体衬底施加应力的第二绝缘膜。

公开(公告)号：US07951686B2

公开(公告)日：2011-05-31

申请号：US12708519

申请日：2010-02-18

申请人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

发明人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

IPC分类号： H01L21/76

CPC分类号： H01L29/045 ,  H01L21/76232 ,  H01L29/7846

摘要： A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.

摘要翻译： 沟槽形成在半导体衬底的表面层中，沟槽围绕有源区。 在半导体器件上沉积由绝缘材料制成的下绝缘膜，下绝缘膜填充沟槽的下部区域并在上部区域留下空的空间。 在其上具有拉伸应力的由绝缘材料制成的上绝缘膜沉积在下绝缘膜上，上绝缘膜填充留在上部空间中的空白空间。 去除沉积在半导体衬底上而不是在沟槽中的上绝缘膜和下绝缘膜。

公开(公告)号：US07701016B2

公开(公告)日：2010-04-20

申请号：US11541782

申请日：2006-10-03

申请人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

发明人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/045 ,  H01L21/76232 ,  H01L29/7846

摘要： A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film has therein a stress generating tensile strain in a surface layer of the active region.

摘要翻译： 在半导体衬底的表面层中形成有围绕有源区的沟槽。 由绝缘材料制成的下绝缘膜填充沟槽的下部区域。 上绝缘膜填充下绝缘膜上方的沟槽的区域。 上部绝缘膜在其中具有在有源区的表面层中的应力产生拉伸应变。

公开(公告)号：US07501686B2

公开(公告)日：2009-03-10

申请号：US11358317

申请日：2006-02-22

申请人： Masaki Okuno ,  Sadahiro Kishii ,  Hiroshi Morioka ,  Masanori Terahara ,  Shigeo Satoh ,  Kaina Suzuki

发明人： Masaki Okuno ,  Sadahiro Kishii ,  Hiroshi Morioka ,  Masanori Terahara ,  Shigeo Satoh ,  Kaina Suzuki

IPC分类号： H01L29/00

CPC分类号： H01L21/76235 ,  H01L21/823878

摘要： A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.

摘要翻译： 公开了一种半导体器件，其包括半导体衬底，设置在半导体衬底的预定位置处的器件区域和隔离器件区域的浅沟槽隔离区域。 浅沟槽隔离区域包括沟槽，设置在沟槽的侧壁的上部的氮化物膜衬垫和设置在沟槽的侧壁的下部的热氧化膜。 浅沟槽隔离被布置成使得设置热氧化膜的浅沟槽隔离区域的第二部分的宽度可以比浅沟槽隔离区域的第一部分的宽度宽， 设置氮化物膜衬垫。