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    GALLIUM NITRIDE DEVICES HAVING LOW OHMIC CONTACT RESISTANCE
    1.
    发明申请
    GALLIUM NITRIDE DEVICES HAVING LOW OHMIC CONTACT RESISTANCE 有权
    具有低OHMIC接触电阻的氮化镓器件

    公开(公告)号：US20140014966A1

    公开(公告)日：2014-01-16

    申请号：US13548305

    申请日：2012-07-13

    申请人： Kamal Tabatabaie ,  William E. Hoke ,  Eduardo M. Chumbes ,  Kevin McCarthy

    发明人： Kamal Tabatabaie ,  William E. Hoke ,  Eduardo M. Chumbes ,  Kevin McCarthy

    IPC分类号： H01L29/20 ,  H01L29/778

    CPC分类号： H01L29/66462 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/7787 ,  H01L29/7789

    摘要： A semiconductor structure having mesa structure comprising: a lower semiconductor layer; an upper semiconductor layer having a higher band gap than, and in direct contact with, the lower semiconductor layer to form a two-dimension electron gas (2DEG) region between the upper semiconductor layer. The 2DEG region has outer edges terminating at sidewalls of the mesa. An additional electron donor layer has a band gap higher than the band gap of the lower layer disposed on sidewall portions of the mesa structure and on the region of the 2DEG region terminating at sidewalls of the mesa. An ohmic contact material is disposed on the electron donor layer. In effect, a sideway HEMT is formed with the electron donor layer, the 2DEG region and the ohmic contact material increasing the concentration of electrons (i.e., lowering ohmic contact resistance) all along the contact between the lower semiconductor layer and the electron donor layer.

    摘要翻译： 一种具有台面结构的半导体结构，包括：下半导体层; 上半导体层具有比下半导体层更高的带隙并且与下半导体层直接接触以在上半导体层之间形成二维电子气（2DEG）区。 2DEG区域具有终止于台面侧壁的外边缘。 另外的电子供体层具有高于设置在台面结构的侧壁部分上的下层的带隙和在台面的侧壁处终止的2DEG区域的区域的带隙。 欧姆接触材料设置在电子供体层上。 实际上，沿着下半导体层和电子供体层之间的接触，形成有电子供体层，2DEG区和欧姆接触材料增加电子浓度（即降低欧姆接触电阻）的侧面HEMT。

    Method for making heterojunction bipolar mixer circuitry
    4.
    发明授权
    Method for making heterojunction bipolar mixer circuitry 失效
    制造异质结双极混频器电路的方法

    公开(公告)号：US5837589A

    公开(公告)日：1998-11-17

    申请号：US774237

    申请日：1996-12-27

    申请人： Brian J. McNamara ,  John P. Wendler ,  Kamal Tabatabaie-Alavi

    发明人： Brian J. McNamara ,  John P. Wendler ,  Kamal Tabatabaie-Alavi

    IPC分类号： H01L27/06 ,  H03D7/02 ,  H01L21/331

    CPC分类号： H03D7/02 ,  H01L27/0605

    摘要： Mixer circuitry having a semiconductor body formed therein mixer circuitry having an oscillator having a heterojunction bipolar transistor and a mixer having a Schottky diode. The heterojunction transistor has a collector region formed in one portion of doped layer of the semiconductor body and the diode has a metal electrode is Schottky contact with another portion of such doped layer. The mixer is includes a diode and a DC biasing circuit, comprising a constant current, for biasing such diode to predetermined operating point substantially invariant with power of an input signal fed to such mixer.

    摘要翻译： 具有形成在其中的混合器电路的混合器电路具有具有异质结双极晶体管的振荡器和具有肖特基二极管的混频器。 异质结晶体管具有形成在半导体本体的掺杂层的一部分中的集电极区域，并且二极管具有金属电极与该掺杂层的另一部分肖特基接触。 混频器包括二极管和直流偏置电路，其包括恒定电流，用于将馈电到这种混频器的输入信号的功率基本上不变地偏置到预定工作点。

    Semiconductor structures having both elemental and compound semiconductor devices on a common substrate
    5.
    发明授权
    Semiconductor structures having both elemental and compound semiconductor devices on a common substrate 有权
    半导体结构在公共衬底上具有元件和复合半导体器件

    公开(公告)号：US07994550B2

    公开(公告)日：2011-08-09

    申请号：US12470633

    申请日：2009-05-22

    申请人： Valery S. Kaper ,  John P. Bettencourt ,  Jeffrey R. LaRoche ,  Kamal Tabatabaie

    发明人： Valery S. Kaper ,  John P. Bettencourt ,  Jeffrey R. LaRoche ,  Kamal Tabatabaie

    IPC分类号： H01L21/02

    CPC分类号： H01L29/78 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/1203 ,  H01L29/12

    摘要： A semiconductor structure comprising: a substrate; a seed layer supported by the substrate; an elemental semiconductor layer disposed over a first portion of the seed layer; and a compound semiconductor layer disposed on a second portion of the seed layer. The first portion of the seed layer is electrically insulated from the second portion of the seed layer. A first semiconductor device is formed in the elemental semiconductor layer. A second semiconductor device is formed in the compound semiconductor layer. The second semiconductor device includes: a first electrode in contact with a first region of the compound semiconductor layer; a second electrode in contact with a second region of the compound semiconductor layer; and a third electrode. The third electrode controls carriers passing in a third region of the compound semiconductor layer disposed between the first region and the second region. A fourth electrode is in electrical contact with the second portion of the seed layer.

    摘要翻译： 一种半导体结构，包括：基板; 由基底支撑的种子层; 设置在种子层的第一部分上的元素半导体层; 以及配置在种子层的第二部分上的化合物半导体层。 种子层的第一部分与种子层的第二部分电绝缘。 在元素半导体层中形成第一半导体器件。 在化合物半导体层中形成第二半导体器件。 第二半导体器件包括：与化合物半导体层的第一区域接触的第一电极; 与所述化合物半导体层的第二区域接触的第二电极; 和第三电极。 第三电极控制通过设置在第一区域和第二区域之间的化合物半导体层的第三区域中的载流子。 第四电极与种子层的第二部分电接触。

    Atomic layer deposition in the formation of gate structures for III-V semiconductor
    6.
    发明授权
    Atomic layer deposition in the formation of gate structures for III-V semiconductor 有权
    原子层沉积形成III-V半导体栅极结构

    公开(公告)号：US07692222B2

    公开(公告)日：2010-04-06

    申请号：US11557354

    申请日：2006-11-07

    申请人： Kamal Tabatabaie ,  Robert B. Hallock

    发明人： Kamal Tabatabaie ,  Robert B. Hallock

    IPC分类号： H01L29/47

    CPC分类号： H01L21/28587 ,  H01L29/66462

    摘要： A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.

    摘要翻译： 一种半导体结构和方法，其中凹部设置在半导体结构的表面部分中，并且电介质膜设置在半导体上并与其接合。 电介质膜具有孔。 电介质膜的一部分设置成与凹部的孔和悬垂下部相邻。 电触头的第一部分设置在电介质膜的相邻部分上，第二部分设置在凹槽的下面部分上，电介质膜的部分设置在电触点的第一部分和第二部分之间 电接触，并且电接触件的第三部分设置在半导体结构中的凹部的底部上并与其接触。 电接触通过在电介质膜上并通过这种电介质膜中的孔的原子层沉积导电材料形成。

    Method for processing semiconductors using a combination of electron beam and optical lithography
    7.
    发明授权
    Method for processing semiconductors using a combination of electron beam and optical lithography 有权
    使用电子束和光学光刻的组合处理半导体的方法

    公开(公告)号：US08754421B2

    公开(公告)日：2014-06-17

    申请号：US13404245

    申请日：2012-02-24

    申请人： Paul J. Duval ,  Kamal Tabatabaie ,  William J. Davis

    发明人： Paul J. Duval ,  Kamal Tabatabaie ,  William J. Davis

    IPC分类号： H01L29/201 ,  H01L21/30

    CPC分类号： H01L21/71 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.

    摘要翻译： 使用光刻法在半导体结构上形成对准标记，以在结构的基板上形成金属对准标记，使用所形成的金属对准标记，以形成利用光刻法形成在基板上的半导体器件的第一特征，以及 使用形成的金属对准标记来形成使用电子束光刻的半导体的第二不同特征。 在一个实施例中，第一特征是欧姆接触，第二特征是肖特基接触，金属对准标记是原子量大于60的难熔金属或难熔金属化合物，例如TaN，并且半导体器件是GaN 半导体器件。 在结构的零层上具有金属对准标记的半导体结构，金属对准标记为TaN，半导体为GaN。

    Method For Processing Semiconductors Using A Combination Of Electron Beam And Optical Lithography
    8.
    发明申请
    Method For Processing Semiconductors Using A Combination Of Electron Beam And Optical Lithography 有权
    使用电子束和光学平版印刷的组合处理半导体的方法

    公开(公告)号：US20130221365A1

    公开(公告)日：2013-08-29

    申请号：US13404245

    申请日：2012-02-24

    申请人： Paul J. Duval ,  Kamal Tabatabaie ,  William J. Davis

    发明人： Paul J. Duval ,  Kamal Tabatabaie ,  William J. Davis

    IPC分类号： H01L29/201 ,  H01L21/30

    CPC分类号： H01L21/71 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.

    摘要翻译： 使用光刻法在半导体结构上形成对准标记，以在结构的基板上形成金属对准标记，使用所形成的金属对准标记，以形成利用光刻法形成在基板上的半导体器件的第一特征，以及 使用形成的金属对准标记来形成使用电子束光刻的半导体的第二不同特征。 在一个实施例中，第一特征是欧姆接触，第二特征是肖特基接触，金属对准标记是原子量大于60的难熔金属或难熔金属化合物，例如TaN，并且半导体器件是GaN 半导体器件。 在结构的零层上具有金属对准标记的半导体结构，金属对准标记为TaN，半导体为GaN。