公开(公告)号：US20090197114A1

公开(公告)日：2009-08-06

申请号：US12254790

申请日：2008-10-20

申请人： Da-Yuan Shih ,  Donald W. Henderson ,  Sung K. Kang ,  Minhua Lu ,  Jae-Woong Nah ,  Kamalesh Srivastava

发明人： Da-Yuan Shih ,  Donald W. Henderson ,  Sung K. Kang ,  Minhua Lu ,  Jae-Woong Nah ,  Kamalesh Srivastava

IPC分类号： B32B15/01 ,  B23K1/20

CPC分类号： B23K1/008 ,  B23K1/0016 ,  B23K1/203 ,  B23K2101/42 ,  C22C13/00 ,  H01L2224/16225 ,  H05K3/3463 ,  Y10T428/12708 ,  Y10T428/12715

摘要： A solder joint comprising a solder capture pad on a substrate having a circuit; and a lead free solder selected from the group comprising Sn—Ag—Cu solder and Sn—Ag solder adhered to the solder capture pad; the solder selected from the group comprising between 0.1 to 2.0% by weight Sb or Bi, and 0.5 to 3.0% Ag. Formation of voids at an interface between the solder and the solder capture pad is suppressed, by including Zn. Interlayer dielectric delamination is suppressed, and electromigration characteristics are greatly improved. Methods for forming solder joints using the solders.

公开(公告)号：US20060009022A1

公开(公告)日：2006-01-12

申请号：US11162468

申请日：2005-09-12

申请人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

发明人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014

摘要： A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

摘要翻译： 用于形成半导体器件的互连结构的方法包括在钝化层中限定通孔，以暴露半导体器件中的顶部金属层。 在钝化层，通孔的侧壁和顶部金属层上形成种子层。 在种子层的暴露部分上形成阻挡层，暴露部分由第一图案化开口限定。 半导体器件被退火以使来自阻挡层的原子扩散到其中的晶种层中，其中退火使种子层的扩散区域相对于种子层的未扩散区域具有改变的电阻率和电极电位 。

公开(公告)号：US20070080455A1

公开(公告)日：2007-04-12

申请号：US11163235

申请日：2005-10-11

申请人： Donna Zupanski-Nielsen ,  William Landers ,  Ian Melville ,  Roger Quon ,  Timothy Daubenspeck ,  Kamalesh Srivastava ,  Mary Cullinan-Scholl ,  Lawrence Clevenger ,  Christopher Muzzy

发明人： Donna Zupanski-Nielsen ,  William Landers ,  Ian Melville ,  Roger Quon ,  Timothy Daubenspeck ,  Kamalesh Srivastava ,  Mary Cullinan-Scholl ,  Lawrence Clevenger ,  Christopher Muzzy

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/13 ,  H01L21/76831 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

摘要： A semiconductor having an insulating layer, a contact pad, a via, and a sacrificial dielectric cap is provided. The contact pad is embedded in the insulating layer, where the contact pad has a top metal layer of copper. The via creates an opening over the top metal layer. The sacrificial dielectric cap is over at least the top metal layer.

摘要翻译： 提供具有绝缘层，接触焊盘，通孔和牺牲电介质盖的半导体。 接触垫嵌入在绝缘层中，其中接触垫具有铜的顶部金属层。 通孔在顶部金属层上形成一个开口。 牺牲绝缘帽至少在顶部金属层之上。

公开(公告)号：US20050167837A1

公开(公告)日：2005-08-04

申请号：US10707892

申请日：2004-01-21

申请人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

发明人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

IPC分类号： H01L23/485 ,  H01L23/58 ,  H01L29/40

CPC分类号： H01L22/32 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05655 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14

摘要： A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.

摘要翻译： 用于集成电路（IC）芯片的耐用芯片焊盘，具有在多个芯片位置具有耐用芯片焊盘的IC芯片的半导体晶片以及在晶片上制造IC芯片的方法。 可以通过探头直接接触耐用的芯片焊盘来探测芯片进行性能测试。

公开(公告)号：US06479884B2

公开(公告)日：2002-11-12

申请号：US09893786

申请日：2001-06-29

申请人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

发明人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

IPC分类号： H01L2358

CPC分类号： H01L21/76808 ,  H01L2221/1063

摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

摘要翻译： 抗蚀剂显影剂可以攻击一些先进的介电材料，例如可以用作集成电路芯片的表面和形成在介电材料表面上的布线层之间的绝缘体的倍半硅氧烷材料。 通过进行抗蚀剂剥离或蚀刻工艺，其中将反应物材料从电介质材料外部供应或释放出来，可以形成非常薄的中间材料的表面保护覆盖层，其不能抵抗显影剂或多种其它材料 这可能会损坏可流动的氧化物材料。 因此，与芯片形成牢固的连接和通孔的双镶嵌工艺可以与具有特别低介电常数的先进电介质相兼容，以最小化导体电容并支持快速的信号传播和抗噪声性，即使导体彼此间隔紧密。

公开(公告)号：US06329280B1

公开(公告)日：2001-12-11

申请号：US09311470

申请日：1999-05-13

申请人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

发明人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L2221/1063

摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

公开(公告)号：US20060081981A1

公开(公告)日：2006-04-20

申请号：US11271760

申请日：2005-11-10

申请人： Julie Biggs ,  Tien-Jen Cheng ,  David Eichstadt ,  Lisa Fanti ,  Jonathan Griffith ,  Randolph Knarr ,  Sarah Knickerbocker ,  Kevin Petrarca ,  Roger Quon ,  Wolfgang Sauter ,  Kamalesh Srivastava ,  Richard Volant

发明人： Julie Biggs ,  Tien-Jen Cheng ,  David Eichstadt ,  Lisa Fanti ,  Jonathan Griffith ,  Randolph Knarr ,  Sarah Knickerbocker ,  Kevin Petrarca ,  Roger Quon ,  Wolfgang Sauter ,  Kamalesh Srivastava ,  Richard Volant

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

公开(公告)号：US20050103636A1

公开(公告)日：2005-05-19

申请号：US10707047

申请日：2003-11-18

申请人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Rosemary Previti-Kelly ,  Roger Quon ,  Kamalesh Srivastava ,  Keith Wong

发明人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Rosemary Previti-Kelly ,  Roger Quon ,  Kamalesh Srivastava ,  Keith Wong

IPC分类号： C25D5/00 ,  C25D5/02 ,  C25D5/12 ,  C25D7/12 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485

CPC分类号： H01L24/13 ,  C25D5/022 ,  C25D5/12 ,  C25D7/123 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2224/29099 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.

摘要翻译： 一种用于半导体输入/输出（I / O）焊盘的选择性电镀的方法包括在半导体衬底上的钝化层上形成钛 - 钨（TiW）层，所述TiW层进一步延伸到形成在钝化层中的开口中 暴露I / O焊盘，使得TiW层覆盖开口的侧壁和I / O焊盘的顶表面。 在TiW层上形成种子层，并且选择性地去除种子层的部分，使得剩余的种子层材料对应于用于I / O焊盘的互连冶金的期望位置。 使用TiW层作为导电电镀介质，在剩余的种子层材料上电镀至少一层金属层。

公开(公告)号：US20090197103A1

公开(公告)日：2009-08-06

申请号：US12254768

申请日：2008-10-20

申请人： Da-Yuan Shih ,  Donald W. Henderson ,  Sung K. Kang ,  Minhua Lu ,  Jae-Woong Nah ,  Kamalesh Srivastava

发明人： Da-Yuan Shih ,  Donald W. Henderson ,  Sung K. Kang ,  Minhua Lu ,  Jae-Woong Nah ,  Kamalesh Srivastava

IPC分类号： B32B15/04 ,  B23K1/20 ,  C22C13/00

CPC分类号： B23K1/0016 ,  B23K1/008 ,  B23K1/203 ,  B23K2101/42 ,  C22C13/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0346 ,  H01L2224/03464 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05613 ,  H01L2224/05618 ,  H01L2224/0562 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/81191 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/35121 ,  H01L2924/3656 ,  H05K3/3463 ,  Y10T428/31678 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/01051 ,  H01L2924/00

摘要： A solder joint comprising a solder capture pad on a substrate having a circuit; and a lead free solder selected from the group comprising Sn—Ag—Cu solder and Sn—Ag solder adhered to the solder capture pad; the solder selected from the group comprising between 0.1 to 2.0% by weight Sb or Bi, and 0.5 to 3.0% Ag. Formation of voids at an interface between the solder and the solder capture pad is suppressed, by including Zn. Interlayer dielectric delamination is suppressed, and electromigration characteristics are greatly improved. Methods for forming solder joints using the solders.

摘要翻译： 一种焊接接头，包括在具有电路的基板上的焊料捕获垫; 以及选自Sn-Ag-Cu焊料和Sn-Ag焊料的焊料的无铅焊料粘附到焊料捕获垫上; 选自包含0.1至2.0重量％的Sb或Bi和0.5至3.0％Ag的组的焊料。 焊料和焊料捕捉垫之间的界面上的空隙形成通过包含Zn而被抑制。 层间电介质分层被抑制，电迁移特性大大提高。 使用焊料形成焊点的方法。

公开(公告)号：US20060249854A1

公开(公告)日：2006-11-09

申请号：US11478933

申请日：2006-06-29

申请人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

发明人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

IPC分类号： H01L23/48

CPC分类号： H01L22/32 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05655 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14

摘要： A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.

摘要翻译： 用于集成电路（IC）芯片的耐用芯片焊盘，具有在多个芯片位置具有耐用芯片焊盘的IC芯片的半导体晶片以及在晶片上制造IC芯片的方法。 可以通过探头直接接触耐用的芯片焊盘来探测芯片进行性能测试。