Sacrificial self-aligned interconnect structures
    1.
    发明授权
    Sacrificial self-aligned interconnect structures 有权
    牺牲自对准互连结构

    公开(公告)号:US07825450B2

    公开(公告)日:2010-11-02

    申请号:US12205019

    申请日:2008-09-05

    IPC分类号: H01L27/108 H01L29/94

    摘要: A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material adjacent to an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A preexisting geometry of the active region is maintained during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer. The interconnect structure hole is filled with polysilicon, the surface of the substrate assembly is planarized, and the nitride layer is removed.

    摘要翻译: 牺牲的自对准多晶硅互连结构形成在与有源区位置相邻并且位于衬底组件的半导体器件下方的绝缘材料的区域中,以便电连接有源区和半导体器件。 在蚀刻形成互连结构的互连结构孔期间维持有源区的预先存在的几何形状并且节省了工艺步骤。 在该方法下,绝缘材料的区域紧邻有源区位置形成。 在有源区上形成氮化物层并保护有源区,同时利用对氮化物层有选择性的蚀刻工艺将互连结构孔部分地蚀刻到与有源区位置相邻的绝缘材料区域内。 互连结构孔填充有多晶硅,衬底组件的表面被平坦化,并且氮化物层被去除。

    Method of making sacrificial self-aligned interconnection structure
    2.
    发明授权
    Method of making sacrificial self-aligned interconnection structure 失效
    制造牺牲自对准互连结构的方法

    公开(公告)号:US06995072B2

    公开(公告)日:2006-02-07

    申请号:US10721147

    申请日:2003-11-25

    摘要: A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A method for making the interconnect structure maintains a preexisting geometry of the active region during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer. The interconnect structure hole is filled with polysilicon, the surface of the substrate assembly is planarized, and the nitride layer is removed.

    摘要翻译: 牺牲的自对准多晶硅互连结构形成在绝缘材料的区域到有源区位置的侧面并且位于衬底组件的半导体器件的下方,以便电连接有源区域和半导体器件。 用于制造互连结构的方法在蚀刻形成互连结构的互连结构孔期间保持有源区的预先存在的几何形状,并且节省了工艺步骤。 在该方法下,绝缘材料的区域紧邻有源区位置形成。 在有源区上形成氮化物层并保护有源区,同时利用对氮化物层有选择性的蚀刻工艺将互连结构孔部分地蚀刻到与有源区位置相邻的绝缘材料区域内。 互连结构孔填充有多晶硅,衬底组件的表面被平坦化,并且氮化物层被去除。

    System for performing thermal reflow operations under high gravity conditions
    3.
    发明授权
    System for performing thermal reflow operations under high gravity conditions 失效
    用于在高重力条件下进行热回流操作的系统

    公开(公告)号:US06747249B2

    公开(公告)日:2004-06-08

    申请号:US10446381

    申请日:2003-05-27

    IPC分类号: C23C1600

    CPC分类号: F27B17/00

    摘要: A thermal reflow processing system has a rotatable structure to which articles having a reflowable surface are attached. The structure is coupled to a drive motor which causes the structure to rotate at speeds which generate centripetal forces in excess of that of gravity. The system is equipped with at least one radiant heat source. As the articles are being subjected to a centripetal force, the surface is heated by the radiant heat source.

    摘要翻译: 热回流处理系统具有可旋转的结构,具有可回流表面的物品被附接到该结构。 该结构联接到驱动马达,其使结构以产生超过重力的向心力的速度旋转。 该系统配备有至少一个辐射热源。 当制品受到向心力时,表面被辐射热源加热。

    Methods, apparatuses and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes

    公开(公告)号:US06645865B2

    公开(公告)日:2003-11-11

    申请号:US10285134

    申请日:2002-10-30

    IPC分类号: H01L21302

    摘要: Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped. The first change in drag force between the substrate assembly and the planarizing medium is preferably detected by measuring a first change in the electrical current through a drive motor driving a substrate holder carrying the substrate assembly and/or a table carrying the polishing pad. The second change in drag force between the substrate assembly and the polishing pad may be identified by detecting a second change in the drive motor current or measuring a second change in the temperature of the planarizing solution or the polishing pad.

    Belt polishing pad method
    5.
    发明授权
    Belt polishing pad method 失效
    皮带抛光垫法

    公开(公告)号:US06409581B1

    公开(公告)日:2002-06-25

    申请号:US09629065

    申请日:2000-07-31

    IPC分类号: B24B100

    CPC分类号: B24B37/26 B24B41/047

    摘要: The present invention comprises a method of chemical-mechanical polishing of a surface on a semiconductor substrate by providing a fixed-abrasive polishing pad; providing a surface to be polished; and providing a chemical polishing solution containing a surface tension-lowering agent that lowers the surface tension of the solution from the nominal surface tension of water to a surface tension that sufficiently wets a hydrophobic surface to be polished such that chemical-mechanical polishing is accomplished. The present invention also comprises pad improvements that mechanically sweep the polishing solution under the pad or that receive polishing solution from the back of the pad such that a tangential and radial shear is placed on the polishing solution as it flows away from the pad.

    摘要翻译: 本发明包括通过提供固定研磨抛光垫对半导体衬底上的表面进行化学机械抛光的方法; 提供要抛光的表面; 并且提供含有表面张力降低剂的化学抛光溶液,其将溶液的表面张力从水的标称表面张力降低到充分润湿要抛光的疏水表面的表面张力,从而实现化学机械抛光。 本发明还包括垫片改进,其将抛光溶液机械地扫过垫片下方或者从垫的背面接收抛光溶液,使得当抛光溶液从衬垫流出时,切向和径向剪切被放置在抛光溶液上。

    Method for conditioning a polishing pad used in chemical-mechanical planarization of semiconductor wafers
    6.
    发明授权
    Method for conditioning a polishing pad used in chemical-mechanical planarization of semiconductor wafers 失效
    用于调整用于半导体晶片的化学机械平面化的抛光垫的方法

    公开(公告)号:US06409577B1

    公开(公告)日:2002-06-25

    申请号:US09867849

    申请日:2001-05-29

    申请人: Karl M. Robinson

    发明人: Karl M. Robinson

    IPC分类号: B24B100

    CPC分类号: B24B53/017 B24B37/04

    摘要: A method for conditioning a polishing pad used in chemical-mechanical planarization of semiconductor wafers. Waste matter on the polishing pad is dissolved with a conditioning solution selected to chemically dissolve the material of the waste matter. The conditioning solution preferably coats the areas on the wafer upon which the waste matter tends to accumulate during planarization. After a desired amount of waste matter is dissolved into the conditioning solution to bring the pad into a desired condition without mechanically abrading the waste matter from the pad, the conditioning solution containing the dissolved waste matter may be removed from the pad.

    摘要翻译: 一种用于调整用于半导体晶片的化学机械平面化的抛光垫的方法。 抛光垫上的废物用选择用于化学溶解废物物质的调理溶液溶解。 调理溶液优选包覆在平坦化期间废物倾向于积聚的晶片上的区域。 在将所需量的废物溶解到调理溶液中以使垫进入所需状态之后,不会从废物中磨碎废物,所以可以从垫中除去含有溶解的废物的调理溶液。

    Methods of polishing materials, methods of slowing a rate of material removal of a polishing process, and methods of forming trench isolation regions
    7.
    发明授权
    Methods of polishing materials, methods of slowing a rate of material removal of a polishing process, and methods of forming trench isolation regions 有权
    抛光材料的方法,减慢抛光工艺的材料去除速率的方法,以及形成沟槽隔离区域的方法

    公开(公告)号:US06386951B2

    公开(公告)日:2002-05-14

    申请号:US09775788

    申请日:2001-02-01

    IPC分类号: C03L1502

    摘要: The invention includes polishing processes, methods of polishing materials, methods for slowing a rate of material removal of a polishing process, and methods of forming trench isolation regions. In one aspect, the invention includes a method comprising: a) forming a material over a surface of a substrate; b) providing a substantially nonporous polishing pad and a chemical composition proximate the material, the material being substantially wettable to the chemical composition, the substrate surface and substantially non-porous polishing pad being substantially non-wettable to the chemical composition; and c) polishing the material with the substantially non-porous polishing pad and the chemical composition. In another aspect, the invention includes a method comprising: a) forming a first silicon dioxide layer over a substrate; b) forming a polysilicon layer over the first silicon dioxide layer, the polysilicon layer having an upper surface; c) forming an opening through the polysilicon layer, through the first silicon dioxide layer, and into the substrate; d) forming a second layer of silicon dioxide within the opening and over the polysilicon layer upper surface, the second layer of silicon dioxide substantially completely filling the opening; and e) polishing the second silicon dioxide from over the polysilicon layer upper surface utilizing a substantially non-porous hydrophobic material polishing pad and a water-comprising chemical composition.

    摘要翻译: 本发明包括抛光工艺,抛光材料的方法,减缓抛光工艺的材料去除速率的方法,以及形成沟槽隔离区域的方法。 一方面,本发明包括一种方法,包括:a)在衬底的表面上形成材料; b)提供基本上无孔的抛光垫和靠近该材料的化学组成,该材料基本上可润湿化学组成,该基材表面和基本上无孔的抛光垫基本上不能润湿该化学组成; 和c)用基本上无孔的抛光垫和化学成分抛光材料。 在另一方面,本发明包括一种方法,包括:a)在衬底上形成第一二氧化硅层; b)在所述第一二氧化硅层上形成多晶硅层,所述多晶硅层具有上表面; c)通过所述多晶硅层形成穿过所述第一二氧化硅层并进入所述衬底的开口; d)在所述开口内和所述多晶硅层上表面上形成第二二氧化硅层,所述第二二氧化硅层基本上完全填充所述开口; 以及e)利用基本上无孔的疏水材料抛光垫和含水的化学组合物从所述多晶硅层上表面上抛光所述第二二氧化硅。

    Method of making a sacrificial self-aligned interconnect structure
    8.
    发明授权
    Method of making a sacrificial self-aligned interconnect structure 有权
    制造牺牲自对准互连结构的方法

    公开(公告)号:US06168986A

    公开(公告)日:2001-01-02

    申请号:US09293369

    申请日:1999-04-16

    IPC分类号: H01L218242

    摘要: A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A method for making the interconnect structure maintains a preexisting geometry of the active region during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer. The interconnect structure hole is filled with polysilicon, the surface of the substrate assembly is planarized, and the nitride layer is removed. The method self-aligns the interconnect structure to the active region location. The nitride layer can be used to protect the active region during sacrificial etching of the interconnect structure during formation of an overlying semiconductor device. A portion of the region of insulating material immediately underlies the interconnect structure to provide over-etch protection. A container capacitor cell is constructed with the method using the interconnect structure as a sacrificial landing pad.

    摘要翻译: 牺牲的自对准多晶硅互连结构形成在绝缘材料的区域到有源区位置的侧面并且位于衬底组件的半导体器件的下方,以便电连接有源区域和半导体器件。 用于制造互连结构的方法在蚀刻形成互连结构的互连结构孔期间保持有源区的预先存在的几何形状,并且节省了工艺步骤。 在该方法下,绝缘材料的区域紧邻有源区位置形成。 在有源区上形成氮化物层并保护有源区,同时利用对氮化物层有选择性的蚀刻工艺将互连结构孔部分地蚀刻到与有源区位置相邻的绝缘材料区域内。 互连结构孔填充有多晶硅,衬底组件的表面被平坦化,并且氮化物层被去除。 该方法将互连结构自对准到活动区域位置。 氮化物层可用于在形成上覆半导体器件期间在互连结构的牺牲蚀刻期间保护有源区。 绝缘材料区域的一部分立即在互连结构的下面,以提供过蚀刻保护。 通过使用互连结构作为牺牲着陆垫的方法来构造容器电容器单元。

    Polishing pad methods of manufacture and use
    9.
    发明授权
    Polishing pad methods of manufacture and use 有权
    抛光垫的制造和使用方法

    公开(公告)号:US6136043A

    公开(公告)日:2000-10-24

    申请号:US294908

    申请日:1999-04-20

    摘要: The present invention is directed to polishing pads useful in determining an end to the useful wear life thereof. In a simple embodiment of the present invention, a polishing pad that is used with slurries is dyed on one side in a manner that causes the dye to permeate the pad to a limited depth that does not cause total coloring. Another embodiment of the present invention involves a fixed abrasive pad that has fixed abrasives embedded into the pad to a selected depth where at least one color level is within the portion of the pad that contains the fixed abrasives. After dyeing the pad, the pad is attached to the polishing platen. During the polishing operation, a color change signals a time to stop the polishing operation and change the pad. With multiple colors in the pad, limited only by the ability to dye the pad with uniform depth levels, characteristic wear patterns can be observed and adjustments made accordingly to prolong and optimize pad life. A pad having voids and optional abrasives incorporated therein is also disclosed. The contents of each void facilitates the detection of the degree to which the polishing pad has been worn during a polishing operation. Substances may be stored within voids that are released by the breach of the voids caused abrasion during the polishing operation. Visual or audible diagnostics resulting from the breaching of voids are useful to control the polishing operation and thus increase yield.

    摘要翻译: 本发明涉及用于确定其有用磨损寿命结束的抛光垫。 在本发明的一个简单实施例中,与浆料一起使用的抛光垫在一侧被染色,使得染料渗透到不会引起全部着色的有限深度的方式。 本发明的另一个实施例涉及一种固定研磨垫,其具有嵌入到垫中的固定研磨剂至选定深度,其中至少一个颜色水平位于包含固定磨料的垫的部分内。 在对该垫进行染色之后,该垫被附着到该研磨台板上。 在抛光操作期间,颜色变化发出指示停止抛光操作并改变垫的时间。 在衬垫中具有多种颜色,仅受到具有均匀深度水平染色垫的能力的限制,可以观察到特征磨损图案并相应地进行调整以延长并优化垫寿命。 还公开了一种具有空隙的衬垫和其中并入的任选的研磨剂。 每个空隙的内容有助于在抛光操作期间检测抛光垫已磨损的程度。 物质可以存储在通过在抛光操作期间由于空隙引起磨损而释放的空隙中。 由于破裂导致的视觉或听觉诊断有助于控制抛光操作,从而提高产量。

    Slurries for mechanical or chemical-mechanical planarization of
microelectronic-device substrate assemblies, and methods and
apparatuses for making and using such slurries
    10.
    发明授权
    Slurries for mechanical or chemical-mechanical planarization of microelectronic-device substrate assemblies, and methods and apparatuses for making and using such slurries 有权
    用于微电子器件基板组件的机械或化学机械平面化的浆料,以及用于制造和使用这种浆料的方法和装置

    公开(公告)号:US6124207A

    公开(公告)日:2000-09-26

    申请号:US144536

    申请日:1998-08-31

    摘要: Slurries used in the manufacturing of microelectronic devices, and apparatuses and methods for making and using such slurries. In one aspect of the invention, a planarizing slurry for planarizing a microelectronic-device substrate assembly is made by fracturing agglomerations of abrasive particles in a first slurry component into smaller agglomerations of abrasive particles or individual abrasive particles. The first slurry component can include water and the abrasive particles. The agglomerations of abrasive particles can be fractured into smaller units by imparting energy to the first slurry component before the first slurry component is mixed with a second slurry component. The agglomerations of abrasive particles are preferably fractured by imparting sonic energy to the first slurry component before it is mixed with the second slurry component. The agglomerations of abrasive particles in the first slurry component may also be fractured by ball milling or highly turbulent pumping. After fracturing the agglomerations of abrasive particles into smaller units, the first slurry component is mixed with the second slurry component. Another aspect of the invention is inhibiting re-agglomeration of the abrasive particles after mixing the first and second slurry components.

    摘要翻译: 用于制造微电子器件的浆料,以及用于制造和使用这种浆料的设备和方法。 在本发明的一个方面,用于平坦化微电子器件衬底组件的平坦化浆料是通过将第一浆料组分中的磨料颗粒的团聚体破碎成更小的磨料颗粒或各个磨料颗粒的聚集而制成的。 第一浆料组分可以包括水和磨料颗粒。 在将第一浆料组分与第二浆料组分混合之前,通过在第一浆料组分上施加能量,可以将磨料颗粒的团聚体破碎成更小的单位。 研磨颗粒的聚集优选在与第二浆料组分混合之前将声能赋予第一浆料组分而断裂。 第一浆料组分中磨料颗粒的聚集也可能通过球磨或高度湍流泵送而断裂。 在将磨料颗粒的团块分解成更小的单元之后,将第一浆料组分与第二浆料组分混合。 本发明的另一方面是在混合第一和第二浆料组分之后抑制磨粒的再附聚。