公开(公告)号：US06303980B1

公开(公告)日：2001-10-16

申请号：US09549276

申请日：2000-04-14

Applicant: Wolfgang Werner ,  Karlheinz Müller ,  Holger Pöhle

Inventor： Wolfgang Werner ,  Karlheinz Müller ,  Holger Pöhle

IPC: H01L2702

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fusible link in an integrated semiconductor circuit and a process for producing the fusible link contemplate the disposition of a fusible link, which is constructed with a cross-sectional constriction as a desired fusing point for its conductor track, in a void. A surface of the void and/or a bare conductor track can be covered with a protection layer, to prevent corrosion. The advantages of such a fusible link are a lower ignition energy and increased reliability. The fusible link may be used as a memory element of a PROM.

Abstract translation: 集成半导体电路中的可熔链路和用于制造可熔连接的工艺的过程考虑到在空隙中构造有作为其导体轨迹的期望的熔合点的横截面收缩的可熔连接件的布置。 空隙和/或裸导体轨道的表面可以用保护层覆盖，以防止腐蚀。 这种可熔连接件的优点是较低的点火能量和更高的可靠性。 可熔链路可以用作PROM的存储元件。

公开(公告)号：US06207517B1

公开(公告)日：2001-03-27

申请号：US09376946

申请日：1999-08-18

Applicant: Karlheinz Müller

Inventor： Karlheinz Müller

IPC: H01L21336

CPC classification number: H01L21/76804 ,  H01L21/266 ,  H01L21/28123 ,  H01L21/76807 ,  H01L21/823878 ,  Y10S438/978

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions. Likewise, the present invention provides a method for fabricating a semiconductor component containing this semiconductor insulation layer.

Abstract translation: 本发明限定了制造半导体绝缘层的方法：首先提供半导体衬底; 通过逐个区域或全部面积施加绝缘层到半导体衬底; 选择性地将杂质离子注入到绝缘层的至少一个预定区域中; 然后选择性地蚀刻绝缘层，从而根据选择性地注入的杂质离子的区域来对绝缘层进行图案化。 同样，本发明提供一种制造含有该半导体绝缘层的半导体部件的方法。

公开(公告)号：US07582948B2

公开(公告)日：2009-09-01

申请号：US11486748

申请日：2006-07-14

Applicant: Karlheinz Müller ,  Klaus Röschlau

Inventor： Karlheinz Müller ,  Klaus Röschlau

IPC: H01L29/00

CPC classification number: H01L29/0649 ,  H01L21/2257 ,  H01L29/732 ,  H01L29/7809

Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.

Abstract translation: 公开了用于生产的集成晶体管和方法。 具体来说，说明了具有从远离主区域的连接区域的方向从主区域延伸的电绝缘隔离沟道的晶体管。 此外，晶体管包括从主区域延伸到远离主区域的连接区域的辅助沟槽。 该晶体管需要小的芯片面积并具有出色的电气特性。

公开(公告)号：US07767528B2

公开(公告)日：2010-08-03

申请号：US11295152

申请日：2005-12-06

Applicant: Karlheinz Müller ,  Klaus Röschlau

Inventor： Karlheinz Müller ,  Klaus Röschlau

IPC: H01L21/336

CPC classification number: H01L29/66712 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7813

Abstract: A field effect transistor (FET) and fabrication method are disclosed. The FET includes a drift region formed in a substrate. A trench adjoins the drift region and contains at least one control region and a connection region. An inversion channel region is isolated from the control region. A portion of the trench extends to the same depth as a second trench that insulates the FET from other components formed in the substrate. Insulating material is disposed between the trench below the control region and the control region. An insulating layer insulates the FET from the substrate. The trench and/or the connection region may extend into the insulating layer or may be isolated from the insulating layer via the drift region.

Abstract translation: 公开了场效应晶体管（FET）及其制造方法。 FET包括形成在衬底中的漂移区域。 沟槽毗邻漂移区域并且包含至少一个控制区域和连接区域。 从控制区域隔离反向沟道区域。 沟槽的一部分延伸到与第二沟槽相同的深度，该第二沟槽将FET与形成在衬底中的其它部件绝缘。 绝缘材料设置在控制区域下方的沟槽和控制区域之间。 绝缘层使FET与衬底绝缘。 沟槽和/或连接区域可以延伸到绝缘层中，或者可以经由漂移区域与绝缘层隔离。

公开(公告)号：US07297590B2

公开(公告)日：2007-11-20

申请号：US10526818

申请日：2003-08-14

Applicant: Karlheinz Müller ,  Johannes Karl Sturm

Inventor： Karlheinz Müller ,  Johannes Karl Sturm

IPC: H01L21/8234

CPC classification number: H01L31/105 ,  H01L27/144 ,  H01L31/18

Abstract: A method for producing an integrated PIN photodiode. The PIN photodiode contains a doped region of a first conduction type near the substrate and a doped region that is remote from the substrate. The doped region that is remote from the substrate has a different construction type than the region near the substrate. In addition, an intermediate region provided that is a range between the doped region remote from the substrate and the doped region near the substrate. The intermediate region is undoped or provided with weak doping.

Abstract translation: 一种集成PIN光电二极管的制造方法。 PIN光电二极管包含在衬底附近具有第一导电类型的掺杂区域和远离衬底的掺杂区域。 远离衬底的掺杂区域具有与衬底附近的区域不同的结构类型。 此外，设置为距离衬底的掺杂区域和衬底附近的掺杂区域之间的范围的中间区域。 中间区未掺杂或具有弱掺杂。

公开(公告)号：US06888226B2

公开(公告)日：2005-05-03

申请号：US10479267

申请日：2002-05-24

Applicant: Klaus Diefenbeck ,  Christian Herzum ,  Jakob Huber ,  Karlheinz Müller

Inventor： Klaus Diefenbeck ,  Christian Herzum ,  Jakob Huber ,  Karlheinz Müller

IPC: H01L29/08 ,  H01L29/36 ,  H01L29/861 ,  H01L29/167 ,  H01L21/331

CPC classification number: H01L29/861 ,  H01L29/0821 ,  H01L29/36

Abstract: A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration that is lower than a dopant concentration of the base layer, and a second layer of a second conductivity type being operative with the first layer in order to form a transition between the first conductivity type and the second conductivity type. A course of a dopant profile at the transition between the base layer and the first layer is set such that in an ESD case a space charge region shifted to the transition between the base layer and the first layer reaches into the base layer.

Abstract translation: 半导体结构包括第一导电类型的基底层，布置在基底层上并且具有低于基底层的掺杂剂浓度的掺杂剂浓度的第一导电类型的第一层和第二导电类型的第二层 导电类型与第一层一起工作，以形成第一导电类型和第二导电类型之间的转变。 在基底层和第一层之间的过渡处的掺杂剂分布的过程被设置为使得在ESD情况下移动到基底层和第一层之间的转变的空间电荷区域到达基底层。

公开(公告)号：US06852598B2

公开(公告)日：2005-02-08

申请号：US10424019

申请日：2003-04-25

Applicant: Karlheinz Müller ,  Klaus Röschlau ,  Cajetan Wagner

Inventor： Karlheinz Müller ,  Klaus Röschlau ,  Cajetan Wagner

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/423

CPC classification number: H01L29/66681 ,  H01L29/42368 ,  H01L29/66674 ,  H01L29/66689

Abstract: A method for the fabrication of a DMOS transistor structure provides the advantage that, through the use of a protective layer, the DMOS transistor structure, which has already been substantially completed, is protected from the adverse effects of further process steps. The DMOS gate electrode is not, as is customary in the prior art, patterned using a single lithography step, but, rather, the patterning of the DMOS gate electrode is split between two lithography steps. In a first lithography step, substantially only the source region of the DMOS transistor structure is opened. Therefore, the electrode layer that is still present can be used as a mask for the subsequent fabrication of the body region.

Abstract translation: 制造DMOS晶体管结构的方法提供的优点是，通过使用保护层，已经基本完成的DMOS晶体管结构被保护免受进一步处理步骤的不利影响。 如现有技术中常规的DMOS栅极电极不是使用单个光刻步骤图案化的，而是DMOS栅电极的图案化在两个光刻步骤之间被分割。 在第一光刻步骤中，基本上只有DMOS晶体管结构的源极区域被打开。 因此，仍然存在的电极层可以用作随后制造身体区域的掩模。

公开(公告)号：US06379990B1

公开(公告)日：2002-04-30

申请号：US09348160

申请日：1999-07-06

Applicant: Karlheinz Müller ,  Stefan Kolb

Inventor： Karlheinz Müller ,  Stefan Kolb

IPC: H01L2100

CPC classification number: B81C1/00158 ,  B81B2201/0235 ,  B81B2203/0315 ,  B81C2201/0136 ,  B81C2203/0136 ,  G01P15/0802

Abstract: A membrane of the micromechanical semiconductor configuration is formed within a cavity. The membrane is formed by a crystalline layer within the substrate or within an epitaxial sequence of layers of the semiconductor configuration arranged on a substrate. The membrane is laid at the edge region on a support and is covered over by a covering layer supported on a counter-support. The support and the counter-support have a different etch rate from the membrane. Wet-chemical etching of the layer sequence with an etchant that is selective to the material of the membrane thus leads to the formation of a cavity around the membrane. Preferably, the layers are formed of differently doped materials.

Abstract translation: 微机械半导体结构的膜形成在空腔内。 膜由衬底内的结晶层或布置在衬底上的半导体结构的外延层序列形成。 膜被放置在支撑件上的边缘区域，并被支撑在反向支撑件上的覆盖层覆盖。 支撑体和反向支撑件具有与膜不同的蚀刻速率。 因此，使用对膜材料有选择性的蚀刻剂对层序进行湿化学蚀刻从而导致在膜周围形成空腔。 优选地，这些层由不同掺杂的材料形成。

公开(公告)号：US06365525B2

公开(公告)日：2002-04-02

申请号：US09730273

申请日：2000-12-05

Applicant: Karlheinz Müller

Inventor： Karlheinz Müller

IPC: H01L2100

CPC classification number: H01L21/76804 ,  H01L21/266 ,  H01L21/28123 ,  H01L21/76807 ,  H01L21/823878 ,  Y10S438/978

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions.

Abstract translation: 本发明限定了制造半导体绝缘层的方法：首先提供半导体衬底; 通过逐个区域或全部面积施加绝缘层到半导体衬底; 选择性地将杂质离子注入到绝缘层的至少一个预定区域中; 然后选择性地蚀刻绝缘层，从而根据选择性地注入的杂质离子的区域来对绝缘层进行图案化。