公开(公告)号：US20130189822A1

公开(公告)日：2013-07-25

申请号：US13357285

申请日：2012-01-24

申请人： Kai Frohberg ,  Torsten Huisinga ,  Katrin Reiche

发明人： Kai Frohberg ,  Torsten Huisinga ,  Katrin Reiche

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/823475 ,  H01L29/7833

摘要： Methods are provided for fabricating integrated circuits that include forming first and second spaced apart gate structures overlying a semiconductor substrate, and forming first and second spaced apart source/drain regions in the semiconductor substrate between the gate structures. A first layer of insulating material is deposited overlying the gate structures and the source/drain regions by a process of atomic layer deposition, and a second layer of insulating material is deposited overlying the first layer by a process of chemical vapor deposition. First and second openings are etched through the second layer and the first layer to expose portions of the source/drain regions. The first and second openings are filled with conductive material to form first and second spaced apart contacts, electrically isolated from each other, in electrical contact with the first and second source/drain regions.

摘要翻译： 提供了用于制造集成电路的方法，其包括形成覆盖半导体衬底的第一和第二间隔开的栅极结构，以及在栅极结构之间的半导体衬底中形成第一和第二间隔开的源/漏区。 通过原子层沉积的过程沉积覆盖栅极结构和源极/漏极区的第一绝缘材料层，并且通过化学气相沉积工艺将第二层绝缘材料沉积在第一层上。 通过第二层和第一层蚀刻第一和第二开口以暴露源/漏区的部分。 第一和第二开口用导电材料填充以形成与第一和第二源极/漏极区域电接触的彼此电隔离的第一和第二间隔开的触点。

公开(公告)号：US08440534B2

公开(公告)日：2013-05-14

申请号：US13104474

申请日：2011-05-10

申请人： Uwe Griebenow ,  Jan Hoentschel ,  Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Frank Feustel ,  Kerstin Ruttloff

发明人： Uwe Griebenow ,  Jan Hoentschel ,  Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Frank Feustel ,  Kerstin Ruttloff

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/6656 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7836

摘要： Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.

公开(公告)号：US20110291292A1

公开(公告)日：2011-12-01

申请号：US13102411

申请日：2011-05-06

申请人： Kai Frohberg ,  Ralf Richter ,  Torsten Huisinga ,  Katrin Reiche

发明人： Kai Frohberg ,  Ralf Richter ,  Torsten Huisinga ,  Katrin Reiche

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/485 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

摘要： In sophisticated semiconductor devices, the contact elements connecting to active semiconductor regions having formed thereabove closely spaced gate electrode structures may be provided on the basis of a liner material so as to reduce the lateral width of the contact opening, while, on the other hand, non-critical contact elements may be formed on the basis of non-reduced lateral dimensions. To this end, at least a first portion of the critical contact element is formed and provided with a liner material prior to forming the non-critical contact element.

摘要翻译： 在复杂的半导体器件中，可以基于衬垫材料提供连接到形成在其上方的紧密间隔的栅电极结构的有源半导体区域的接触元件，以便减小接触开口的横向宽度，而另一方面， 非临界接触元件可以基于非减小的横向尺寸形成。 为此，临界接触元件的至少第一部分形成并在形成非关键接触元件之前设置有衬垫材料。

公开(公告)号：US20100190309A1

公开(公告)日：2010-07-29

申请号：US12754359

申请日：2010-04-05

申请人： Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Uwe Griebenow

发明人： Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Uwe Griebenow

IPC分类号： H01L21/336

CPC分类号： H01L21/28123 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575

摘要： By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions.

摘要翻译： 通过在高能注入工艺期间在先进的半导体器件的栅电极结构上提供注入阻挡材料，可以实现相对于晶体管的沟道区所需的屏蔽效应。 在稍后的制造阶段中，可以移除注入阻挡部分以将栅极电极的高度降低到期望的水平，以便在层间电介质材料的沉积期间增强工艺条件，从而显着降低产生不规则性的风险，例如 在层间电介质材料中，甚至在密集装填区域也是空隙。

公开(公告)号：US20090243049A1

公开(公告)日：2009-10-01

申请号：US12272273

申请日：2008-11-17

申请人： Kai Frohberg ,  Uwe Griebenow ,  Katrin Reiche ,  Heike Berthold

发明人： Kai Frohberg ,  Uwe Griebenow ,  Katrin Reiche ,  Heike Berthold

IPC分类号： H01L21/3115 ,  H01L23/58

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount of stressed dielectric material may be obtained above other transistors by performing a further deposition process. Hence, the negative effect of the highly stressed dielectric material for specific transistors, for instance in densely packed device regions, may be significantly reduced by depositing the highly stressed dielectric material in two steps with an intermediate relaxation implantation process.

摘要翻译： 应力松弛注入工艺的增强的效率可以通过沉积厚度较小的第一层并在某些器件区域放松应力松弛注入工艺，从而获得在考虑的晶体管附近获得增加量的基本上松弛的电介质材料，其中期望的 通过进行另外的沉积工艺，可以在其它晶体管之上获得大量的应力介电材料。 因此，通过用中间松弛注入工艺在两个步骤中沉积高应力电介质材料，可以显着地降低高应力电介质材料对特定晶体管（例如密集封装器件区域）的负面影响。

公开(公告)号：US20090108336A1

公开(公告)日：2009-04-30

申请号：US12115627

申请日：2008-05-06

申请人： Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Uwe Griebenow

发明人： Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Uwe Griebenow

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28123 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575

摘要： By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions.

摘要翻译： 通过在高能注入工艺期间在先进的半导体器件的栅电极结构上提供注入阻挡材料，可以实现相对于晶体管的沟道区所需的屏蔽效应。 在稍后的制造阶段中，可以移除注入阻挡部分以将栅极电极的高度降低到期望的水平，以便在层间电介质材料的沉积期间增强工艺条件，从而显着降低产生不规则性的风险，例如 在层间电介质材料中，甚至在密集装填区域也是空隙。

公开(公告)号：US08536052B2

公开(公告)日：2013-09-17

申请号：US13208835

申请日：2011-08-12

申请人： Jens Heinrich ,  Kai Frohberg ,  Katrin Reiche

发明人： Jens Heinrich ,  Kai Frohberg ,  Katrin Reiche

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/76844 ,  H01L21/76855 ,  H01L23/53266 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： When forming a metal silicide within contact openings in complex semiconductor devices, a silicidation of sidewall surface areas of the contact openings may be initiated by forming a silicon layer therein, thereby reducing unwanted diffusion of the refractory metal species into the laterally adjacent dielectric material. In this manner, superior reliability and electrical performance of the resulting contact elements may be achieved on the basis of a late silicide process.

摘要翻译： 当在复合半导体器件的接触开口内形成金属硅化物时，可以通过在其中形成硅层来引发接触开口的侧壁表面区域的硅化，从而减少难熔金属物质进入横向相邻电介质材料的不想要的扩散。 以这种方式，可以基于后期硅化物工艺实现所得到的接触元件的优异的可靠性和电性能。

公开(公告)号：US08492217B2

公开(公告)日：2013-07-23

申请号：US13237011

申请日：2011-09-20

申请人： Kai Frohberg ,  Dominik Olligs ,  Daniel Prochnow ,  Katrin Reiche

发明人： Kai Frohberg ,  Dominik Olligs ,  Daniel Prochnow ,  Katrin Reiche

IPC分类号： H01L21/8238

CPC分类号： H01L29/665 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831 ,  H01L29/6659 ,  H01L29/7833

摘要： Disclosed herein are various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts. In one example, one method disclosed herein includes forming a layer of insulating material above a semiconducting substrate, wherein the layer of material has a first thickness, forming a plurality of contact openings in the layer of material having the first thickness and forming an organic material in at least a portion of each of the contact openings. This illustrative method further includes the steps of, after forming the organic material, performing an etching process to reduce the first thickness of the layer of insulating material to a second thickness that is less than the first thickness, after performing the etching process, removing the organic material from the contact openings and forming a conductive contact in each of the contact openings.

摘要翻译： 本文公开了形成具有减小的尺寸的导电触点和结合这种导电触点的各种半导体器件的各种方法。 在一个示例中，本文公开的一种方法包括在半导体衬底上形成绝缘材料层，其中材料层具有第一厚度，在具有第一厚度的材料层中形成多个接触开口并形成有机材料 在每个接触开口的至少一部分中。 该说明性方法还包括以下步骤：在形成有机材料之后，进行蚀刻工艺，以在绝缘材料层的第一厚度减小至小于第一厚度的第二厚度之后，在进行蚀刻工艺之后， 来自接触开口的有机材料，并在每个接触开口中形成导电接触。

公开(公告)号：US20120313176A1

公开(公告)日：2012-12-13

申请号：US13154548

申请日：2011-06-07

申请人： Kai Frohberg ,  Dominik Olligs ,  Jens Heinrich ,  Katrin Reiche

发明人： Kai Frohberg ,  Dominik Olligs ,  Jens Heinrich ,  Katrin Reiche

IPC分类号： H01L27/088 ,  H01L21/768

CPC分类号： H01L21/823475 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823871

摘要： Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.

摘要翻译： 通常，本文公开的主题涉及现代复杂的半导体器件及其形成方法，其中基于掩埋的次级金属化的电路元件之间的电互连可以提供改善的晶体管密度。 本文公开的一种说明性方法包括在半导体器件的第一和第二晶体管元件上形成接触电介质层，并且在形成接触电介质层之后，在接触电介质层的上表面下方形成掩埋导电元件，导电元件提供 第一和第二晶体管元件之间的电连接。

公开(公告)号：US20120161324A1

公开(公告)日：2012-06-28

申请号：US13208835

申请日：2011-08-12

申请人： Jens Heinrich ,  Kai Frohberg ,  Katrin Reiche

发明人： Jens Heinrich ,  Kai Frohberg ,  Katrin Reiche

IPC分类号： H01L23/482 ,  H01L21/26

CPC分类号： H01L21/28518 ,  H01L21/76844 ,  H01L21/76855 ,  H01L23/53266 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： When forming a metal silicide within contact openings in complex semiconductor devices, a silicidation of sidewall surface areas of the contact openings may be initiated by forming a silicon layer therein, thereby reducing unwanted diffusion of the refractory metal species into the laterally adjacent dielectric material. In this manner, superior reliability and electrical performance of the resulting contact elements may be achieved on the basis of a late silicide process.

摘要翻译： 当在复合半导体器件的接触开口内形成金属硅化物时，可以通过在其中形成硅层来引发接触开口的侧壁表面区域的硅化，从而减少难熔金属物质进入横向相邻电介质材料的不想要的扩散。 以这种方式，可以基于后期硅化物工艺实现所得到的接触元件的优异的可靠性和电性能。