公开(公告)号：US08995748B2

公开(公告)日：2015-03-31

申请号：US13375880

申请日：2010-06-01

申请人： Tsunehiro Sakai ,  Shigeki Kurihara ,  Yutaka Tandai ,  Tamao Ishikawa ,  Yuichi Hamamura ,  Tomohiro Funakoshi ,  Seiji Isogai ,  Katsuhiko Ichinose

发明人： Tsunehiro Sakai ,  Shigeki Kurihara ,  Yutaka Tandai ,  Tamao Ishikawa ,  Yuichi Hamamura ,  Tomohiro Funakoshi ,  Seiji Isogai ,  Katsuhiko Ichinose

IPC分类号： G06T7/00 ,  G01N21/95 ,  H01L21/66

CPC分类号： G06T7/001 ,  G01N21/9501 ,  G06T7/30 ,  G06T2200/24 ,  G06T2207/10056 ,  G06T2207/30148 ,  H01L22/12 ,  H01L22/20

摘要： A defect image processing apparatus uses a normalized cross correlation to image-match a layout image (52) acquired from a design data with an image acquired by removing, from a defect image (53), the defect area portions thereof, and displays, as a result of that matching, a layout image and defect image (54) on the display device. In the displayed layout image & defect image (54), not only the layout image, the layer of which is the same as that of the defect image (53), but also a layout image of another layer is displayed superimposed on the defect image (53). This makes it easier to analyze the factor of a systematic defect having occurred due to a positional relationship with another layer.

摘要翻译： 缺陷图像处理装置使用归一化互相关，将从设计数据获取的布局图像（52）图像匹配到通过从缺陷图像（53）中删除其缺陷区域部分而获取的图像，并将其显示为 该匹配的结果，布局图像和缺陷图像（54）在显示装置上。 在显示的布局图像和缺陷图像（54）中，不仅叠加在缺陷图像上显示其图层与缺陷图像（53）相同的布局图像，而且还显示另一层的布局图像 （53）。 这使得更容易分析由于与另一层的位置关系而发生的系统缺陷的因素。

公开(公告)号：US20120141011A1

公开(公告)日：2012-06-07

申请号：US13375880

申请日：2010-06-01

申请人： Tsunehiro Sakai ,  Shigeki Kurihara ,  Yutaka Tandai ,  Tamao Ishikawa ,  Yuichi Hamamura ,  Tomohiro Funakoshi ,  Seiji Isogai ,  Katsuhiko Ichinose

发明人： Tsunehiro Sakai ,  Shigeki Kurihara ,  Yutaka Tandai ,  Tamao Ishikawa ,  Yuichi Hamamura ,  Tomohiro Funakoshi ,  Seiji Isogai ,  Katsuhiko Ichinose

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G01N21/9501 ,  G06T7/30 ,  G06T2200/24 ,  G06T2207/10056 ,  G06T2207/30148 ,  H01L22/12 ,  H01L22/20

摘要： A defect image processing apparatus uses a normalized cross correlation to image-match a layout image (52) acquired from a design data with an image acquired by removing, from a defect image (53), the defect area portions thereof, and displays, as a result of that matching, a layout image and defect image (54) on the display device. In the displayed layout image & defect image (54), not only the layout image, the layer of which is the same as that of the defect image (53), but also a layout image of another layer is displayed superimposed on the defect image (53). This makes it easier to analyze the factor of a systematic defect having occurred due to a positional relationship with another layer.

摘要翻译： 缺陷图像处理装置使用归一化互相关，将从设计数据获取的布局图像（52）图像匹配到通过从缺陷图像（53）中删除其缺陷区域部分而获取的图像，并将其显示为 该匹配的结果，布局图像和缺陷图像（54）在显示装置上。 在显示的布局图像和缺陷图像（54）中，不仅叠加在缺陷图像上显示其图层与缺陷图像（53）相同的布局图像，而且还显示另一层的布局图像 （53）。 这使得更容易分析由于与另一层的位置关系而发生的系统缺陷的因素。

公开(公告)号：US20090039427A1

公开(公告)日：2009-02-12

申请号：US12251536

申请日：2008-10-15

申请人： Akihiro SHIMIZU ,  Nagatoshi Ooki ,  Yusuke Nonaka ,  Katsuhiko Ichinose

发明人： Akihiro SHIMIZU ,  Nagatoshi Ooki ,  Yusuke Nonaka ,  Katsuhiko Ichinose

IPC分类号： H01L29/78

CPC分类号： H01L29/7845 ,  H01L21/0217 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.

摘要翻译： 半导体器件包括n沟道导电型FET，其具有形成在半导体衬底的主表面上的第一区域中的沟道形成区域和形成在主表面的第二区域中的沟道形成区域的ap沟道导电型FET， 第二区域与第一区域不同。 n沟道FET的栅电极的杂质浓度的杂质浓度大于p沟道FET的栅电极的杂质浓度，从而在沟道形成区域中的漏极电流的流动方向产生拉伸应力 的n沟道FET。 n沟道FET的沟道形成区域中的漏极电流的流动方向的拉伸应力大于p沟道FET的沟道形成区域中的漏极电流的流动方向的拉伸应力。

公开(公告)号：US20070018327A1

公开(公告)日：2007-01-25

申请号：US11529481

申请日：2006-09-29

申请人： Tsuyoshi Fujiwara ,  Masahiro Ushiyama ,  Katsuhiko Ichinose ,  Naohumi Ohashi ,  Tetsuo Saito

发明人： Tsuyoshi Fujiwara ,  Masahiro Ushiyama ,  Katsuhiko Ichinose ,  Naohumi Ohashi ,  Tetsuo Saito

IPC分类号： H01L23/52

CPC分类号： H01L21/76834 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/76816 ,  H01L21/76828 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823828 ,  H01L21/823871 ,  H01L24/11 ,  H01L27/0629 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10894 ,  H01L28/24 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.

摘要翻译： 在制造具有高性能和高可靠性的半导体器件中，在400℃的衬底温度下形成用于自对准的氮化硅膜17，该膜形成为覆盖MISFET的栅电极。 以上，使用包括甲硅烷和氮的原料气体的等离子体CVD。 构成钝化膜的氮化硅膜44通过使用包括甲硅烷，氨和氮的原料气体的等离子体CVD在基板温度约350℃下形成。 氮化硅膜17中所含的氢含量小于氮化硅膜44中所含的氢含量，可以抑制从氮化硅膜17释放氢。

公开(公告)号：US07163886B2

公开(公告)日：2007-01-16

申请号：US10917289

申请日：2004-08-13

申请人： Tsuyoshi Fujiwara ,  Masahiro Ushiyama ,  Katsuhiko Ichinose ,  Naohumi Ohashi ,  Tetsuo Saito

发明人： Tsuyoshi Fujiwara ,  Masahiro Ushiyama ,  Katsuhiko Ichinose ,  Naohumi Ohashi ,  Tetsuo Saito

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/76816 ,  H01L21/76828 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823828 ,  H01L21/823871 ,  H01L24/11 ,  H01L27/0629 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10894 ,  H01L28/24 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.

公开(公告)号：US07115954B2

公开(公告)日：2006-10-03

申请号：US10363065

申请日：2001-06-29

申请人： Akihiro Shimizu ,  Nagatoshi Ooki ,  Yusuke Nonaka ,  Katsuhiko Ichinose

发明人： Akihiro Shimizu ,  Nagatoshi Ooki ,  Yusuke Nonaka ,  Katsuhiko Ichinose

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7845 ,  H01L21/0217 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.

摘要翻译： 半导体器件具有n沟道导电型场效应晶体管，其具有形成在半导体衬底的一个主表面上的第一区域中的沟道形成区域和具有形成在第二区域中的沟道形成区域的ap沟道导电型场效应晶体管， 半导体衬底的主表面，该第二区域与第一区域不同。 在n沟道导电型场效应晶体管的沟道形成区域中产生的内应力与在p沟道导电型场效应晶体管的沟道形成区域中产生的内应力不同。 在n沟道导电型场效应晶体管的沟道形成区域中产生的内应力是拉伸应力，而在p沟道导电型场效应晶体管的沟道形成区域中产生的内应力是压应力。

公开(公告)号：US06933564B2

公开(公告)日：2005-08-23

申请号：US10352022

申请日：2003-01-28

申请人： Youhei Yanagida ,  Katsuhiko Ichinose ,  Tomohiro Saito ,  Shinichiro Mitani

发明人： Youhei Yanagida ,  Katsuhiko Ichinose ,  Tomohiro Saito ,  Shinichiro Mitani

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/76

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： An impurity ion of a polarity opposite to that of an impurity ion forming an n-type diffusion layer is implanted into a lower portion of the n-type diffusion region in a region, in which n-channel type MISFET is to be formed, vertically with respect to a main surface of a semiconductor to form a first p-type pocket layer. Subsequently, an impurity of a p conduction type is implanted into a region between the n-type diffusion region and the first p-type pocket layer obliquely relative to the main surface of the semiconductor substrate to form a second p-type pocket layer. In this arrangement, the concentration of the impurity ion forming the second p-type pocket layer is made higher than the concentration of the impurity ion used to form the first p-type pocket layer.

摘要翻译： 与形成n型扩散层的杂质离子的极性相反的杂质离子注入到要形成n沟道型MISFET的区域中的n型扩散区的下部 相对于半导体的主表面形成第一p型袋层。 随后，相对于半导体衬底的主表面倾斜地，在n型扩散区和第一p型杂质层之间的区域中注入p导电类型的杂质，形成第二p型袋层。 在这种布置中，形成第二p型袋层的杂质离子的浓度高于用于形成第一p型袋层的杂质离子的浓度。

公开(公告)号：US06905982B2

公开(公告)日：2005-06-14

申请号：US10477539

申请日：2002-04-19

申请人： Hidenori Sato ,  Katsuhiko Ichinose ,  Yukino Ishii ,  Tomoko Jinbo

发明人： Hidenori Sato ,  Katsuhiko Ichinose ,  Yukino Ishii ,  Tomoko Jinbo

IPC分类号： H01L21/8247 ,  C23C16/34 ,  C23C16/452 ,  H01L21/28 ,  H01L21/318 ,  H01L21/60 ,  H01L21/8238 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L27/115 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/31

CPC分类号： H01L21/0217 ,  C23C16/345 ,  C23C16/452 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/3185 ,  H01L21/76897 ,  H01L27/1052 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A CVD device (100) used for depositing a silicon nitride has a structure in which a hot wall furnace (103) for thermally degrading a source gas and a chamber (101) for forming a film over a surface of a wafer (1) are separated from each other. The hot wall furnace (103) for thermally degrading the source gas is provided above the chamber (101), and a heater (104) capable of setting the inside of the furnace at a high temperature atmosphere of approximately 1200° C. is provided at the outer periphery thereof. The source gas, supplied to the hot wall furnace (103) through pipes (105) and (106), is thermally degraded in this furnace in advance, and degraded components thereof are supplied on a stage (102) of the chamber (101) to form a film on the surface of the wafer (1).

摘要翻译： 用于沉积氮化硅的CVD装置（100）具有如下结构：在晶片（1）的表面上用于使源气体热降解的热壁炉（103）和用于形成膜的室（101） 彼此分离。 用于使源气体热降解的热壁炉（103）设置在室（101）的上方，并且能够在大约1200℃的高温气氛下将炉内部设置的加热器（104）设置在 其外围。 通过管道（105）和（106）供应到热壁炉（103）的源气体预先在该炉中热劣化，并且将其劣化的组分供应到室（101）的台（102）上， 以在晶片（1）的表面上形成膜。

公开(公告)号：US06706582B2

公开(公告)日：2004-03-16

申请号：US10147045

申请日：2002-05-17

申请人： Youhei Yanagida ,  Katsuhiko Ichinose ,  Tomohiro Saito ,  Shinichiro Mitani

发明人： Youhei Yanagida ,  Katsuhiko Ichinose ,  Tomohiro Saito ,  Shinichiro Mitani

IPC分类号： H01L218234

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： An impurity ion of a polarity opposite to that of an impurity ion forming an n-type diffusion layer is implanted into a lower portion of the n-type diffusion region in a region, in which n-channel type MISFET is to be formed, vertically with respect to a main surface of a semiconductor to form a first p-type pocket layer. Subsequently, an impurity of a p conduction type is implanted into a region between the n-type diffusion region and the first p-type pocket layer obliquely relative to the main surface of the semiconductor substrate to form a second p-type pocket layer. In this arrangement, the concentration of the impurity ion forming the second p-type pocket layer is made higher than the concentration of the impurity ion used to form the first p-type pocket layer.

摘要翻译： 与形成n型扩散层的杂质离子的极性相反的杂质离子注入到要形成n沟道型MISFET的区域中的n型扩散区的下部 相对于半导体的主表面形成第一p型袋层。 随后，相对于半导体衬底的主表面倾斜地，在n型扩散区和第一p型杂质层之间的区域中注入p导电类型的杂质，形成第二p型袋层。 在这种布置中，形成第二p型袋层的杂质离子的浓度高于用于形成第一p型袋层的杂质离子的浓度。

公开(公告)号：US07705402B2

公开(公告)日：2010-04-27

申请号：US12190433

申请日：2008-08-12

申请人： Akihiro Shimizu ,  Nagatoshi Ooki ,  Yusuke Nonaka ,  Katsuhiko Ichinose

发明人： Akihiro Shimizu ,  Nagatoshi Ooki ,  Yusuke Nonaka ,  Katsuhiko Ichinose

IPC分类号： H01L27/092

CPC分类号： H01L29/7845 ,  H01L21/0217 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.

摘要翻译： 半导体器件包括n沟道导电型FET，其具有形成在半导体衬底的主表面上的第一区域中的沟道形成区域和形成在主表面的第二区域中的沟道形成区域的ap沟道导电型FET， 第二区域与第一区域不同。 n沟道FET的栅电极的杂质浓度的杂质浓度大于p沟道FET的栅电极的杂质浓度，从而在沟道形成区域中的漏极电流的流动方向产生拉伸应力 的n沟道FET。 n沟道FET的沟道形成区域中的漏极电流的流动方向的拉伸应力大于p沟道FET的沟道形成区域中的漏极电流的流动方向的拉伸应力。