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1.发明授权公开(公告)号：US08008209B2
公开(公告)日：2011-08-30
申请号：US11877965
申请日：2007-10-24
IPC分类号： H01L21/311 , H01L21/302 , H01L21/461 , C03C15/00 , C03C25/68 , C23F3/00
CPC分类号： H01L21/31116 , H01L21/67069 , H01L21/67248 , Y10S438/978
摘要： A technique is described whereby temperature gradients are created within a semiconductor wafer. Temperature sensitive etching and/or deposition processes are then employed. These temperature sensitive processes proceed at different rates in regions with different temperatures. To reduce pinch off in etching processes, a temperature sensitive etch process is selected and a temperature gradient is created between the surface and subsurface of a wafer such that the etching process proceeds more slowly at the surface than deeper in the wafer. This reduces “crusting” of solid reaction products at trench openings, thereby eliminating pinch off in many cases. Similar temperature-sensitive deposition processes can be employed to produce void-free high aspect ratio conductors and trench fills.
摘要翻译： 描述了在半导体晶片内产生温度梯度的技术。 然后采用温度敏感的蚀刻和/或沉积工艺。 这些温度敏感过程在不同温度的区域中以不同的速率进行。 为了减少蚀刻过程中的夹断，选择温度敏感的蚀刻工艺，并且在晶片的表面和次表面之间产生温度梯度，使得蚀刻工艺在表面上比在晶片更深地进行得更慢。 这减少了沟槽开口处的固体反应产物的“结壳”，从而在许多情况下消除了夹断。 可以使用类似的温度敏感的沉积工艺来产生无空隙的高纵横比导体和沟槽填充物。
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公开(公告)号：US07879717B2
公开(公告)日：2011-02-01
申请号：US12140854
申请日：2008-06-17
申请人： Elbert E. Huang , Kaushik A. Kumar , Kelly Malone , Dirk Pfeiffer , Muthumanickam Sankarapandian , Christy S. Tyberg
发明人： Elbert E. Huang , Kaushik A. Kumar , Kelly Malone , Dirk Pfeiffer , Muthumanickam Sankarapandian , Christy S. Tyberg
IPC分类号： H01L21/00
CPC分类号： H01L21/76801 , H01L21/76807 , H01L21/76828 , H01L21/76829 , H01L21/76835 , Y10S438/97
摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.
摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括由具有组成SivNwCxOyHz的聚合物材料构成的掩埋蚀刻停止层，其中0.05和n1E; v和n1E; 0.8,0和n1E; w和n1E;0.9,0.05≤n1E; x和nlE; 0.8,0和nlE; y＆nlE; 0.3,0.05＆ 对于v + w + x + y + z = 1，z＆nlE; 0.8。 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。
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公开(公告)号：US07851919B2
公开(公告)日：2010-12-14
申请号：US12701045
申请日：2010-02-05
IPC分类号： H01L21/40
CPC分类号： H01L23/5329 , H01L21/76837 , H01L21/76885 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.
摘要翻译： 公开了包括金属互连的金属互连和IC芯片。 该方法的一个实施例可以包括提供直到并包括中间线（MOL）层的集成电路（IC）芯片，MOL层包括定位在第一电介质内的触点; 使第一电介质凹陷，使得接触延伸超过第一电介质的上表面; 在所述第一电介质上形成第二电介质，使得所述第二电介质围绕所述接触的至少一部分，所述第二电介质具有比所述第一电介质更低的介电常数; 在所述第二电介质上形成平坦化层; 通过平坦化层形成开口并进入到接触件的第二电介质中; 并在开口中形成金属以形成金属互连。
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公开(公告)号：US07541277B1
公开(公告)日：2009-06-02
申请号：US12112457
申请日：2008-04-30
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a dielectric cap layer over an interconnect layer formed by a back-end-of-the-line (BEOL) interconnect process, the interconnect process including: lithography, reactive ion etching (RIE), metal filling of BEOL conductors, and chemical-mechanical polishing (CMP), wherein a sacrificial material resides between conductors of the interconnect layer, and wherein the dielectric cap layer is made porous through an oxidation process.
摘要翻译： 一种用于在由后端（BEOL）互连工艺形成的互连层上形成电介质盖层的方法，所述互连工艺包括光刻，反应离子蚀刻（RIE），BEOL导体的金属填充， 和化学机械抛光（CMP），其中牺牲材料位于互连层的导体之间，并且其中电介质盖层通过氧化工艺制成多孔的。
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公开(公告)号：US20090096056A1
公开(公告)日：2009-04-16
申请号：US11869999
申请日：2007-10-10
IPC分类号： H01L23/467 , H01L21/764
CPC分类号： H01L23/467 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.
摘要翻译： 用于形成它的结构和方法。 半导体芯片包括衬底和晶体管。 芯片在衬底上包括N个互连层，N是正整数。 该芯片包括N个互连层内的冷却管道系统。 冷却管系统不包括任何固体或液体材料。 给定冷却管系统中的任何第一点和任何第二点，存在连接第一和第二点并且完全在冷却管系统内的连续路径。 冷却管系统的第一部分与晶体管重叠。 冷却管系统的第二部分高于衬底并且低于顶部互连层。 第二部分与周围环境直接物理接触。
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6.发明申请公开(公告)号：US20090014868A1
公开(公告)日：2009-01-15
申请号：US11775464
申请日：2007-07-10
CPC分类号： H01L21/768 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing an IC chip in portions for later combining and a related structure are disclosed. In one embodiment, the method includes: fabricating a first portion of the IC chip, the first portion including a structure from a selected level of back-end-of-line (BEOL) processing up to an end of the BEOL processing, the first portion providing a specific functionality when combined with a second portion of the IC chip, fabricating the second portion of the IC chip, the second portion including a structure from a device level of the IC chip up to the selected level of the BEOL processing, the second portion having structure providing generic IC chip functionality. The fabrication of the portions may occur at a single location or different locations, and the combining may occur at the same location or different location as one or more of the fabrication processes.
摘要翻译： 公开了用于稍后组合的部分制造IC芯片的方法和相关结构。 在一个实施例中，该方法包括：制造IC芯片的第一部分，第一部分包括从所选择的后端行（BEOL）处理水平到BEOL处理结束的结构，第一部分 当与IC芯片的第二部分组合时提供特定功能的部分，制造IC芯片的第二部分，第二部分包括从IC芯片的器件级直到BEOL处理的所选级别的结构， 第二部分具有提供通用IC芯片功能的结构。 部分的制造可以在单个位置或不同位置处发生，并且组合可以在与一个或多个制造过程相同的位置或不同位置处发生。
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7.发明申请公开(公告)号：US20080197495A1
公开(公告)日：2008-08-21
申请号：US12106396
申请日：2008-04-21
申请人： Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca , Vidhya Ramachandran , Theodorus E. Standaert
发明人： Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca , Vidhya Ramachandran , Theodorus E. Standaert
IPC分类号： H01L23/48
CPC分类号： H01L21/76834 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.
摘要翻译： 半导体结构包括形成在层间电介质（ILD）层内的多个导电线和形成在ILD层和导电线之上的非平面覆盖层，其中覆盖层相对于导电线在第 导线。
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公开(公告)号：US07397081B2
公开(公告)日：2008-07-08
申请号：US10905041
申请日：2004-12-13
申请人： Huilong Zhu , Lawrence A. Clevenger , Omer H. Dokumaci , Kaushik A. Kumar , Carl J. Radens , Dureseti Chidambarrao
发明人： Huilong Zhu , Lawrence A. Clevenger , Omer H. Dokumaci , Kaushik A. Kumar , Carl J. Radens , Dureseti Chidambarrao
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/1083 , H01L29/66795
摘要： A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate region, wherein the semiconductor region is electrically insulated from the gate region by the gate dielectric region, wherein the semiconductor region comprises a channel region and first and second source/drain regions, wherein the channel region is sandwiched between the first and second source/drain regions, wherein the first and second source/drain regions are aligned with the gate region, wherein the channel region and the gate dielectric region (i) share an interface surface which is essentially perpendicular to a top surface of the substrate, and (ii) do not share any interface surface that is essentially parallel to a top surface of the substrate.
摘要翻译： 一种新颖的晶体管结构及其制造方法。 晶体管结构包括（a）衬底和（b）衬底上的半导体区域，栅极介电区域和栅极区域，其中栅极电介质区域夹在半导体区域和栅极区域之间，其中半导体区域 通过所述栅极电介质区域与所述栅极区域电绝缘，其中所述半导体区域包括沟道区域和第一和第二源极/漏极区域，其中所述沟道区域夹在所述第一和第二源极/漏极区域之间，其中所述第一和/ 第二源极/漏极区域与栅极区域对准，其中沟道区域和栅极电介质区域（i）共享基本上垂直于衬底顶表面的界面，以及（ii）不共享任何界面表面 其基本上平行于衬底的顶表面。
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公开(公告)号：US07187081B2
公开(公告)日：2007-03-06
申请号：US10699238
申请日：2003-10-31
申请人： Elbert E. Huang , Kaushik A. Kumar , Kelly Malone , Dirk Pfeiffer , Muthumanickam Sankarapandian , Christy S. Tyberg
发明人： Elbert E. Huang , Kaushik A. Kumar , Kelly Malone , Dirk Pfeiffer , Muthumanickam Sankarapandian , Christy S. Tyberg
IPC分类号： H01L29/40
CPC分类号： H01L21/76801 , H01L21/76807 , H01L21/76828 , H01L21/76829 , H01L21/76835 , Y10S438/97
摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.
摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8,0 <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.8; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。
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公开(公告)号：US08664012B2
公开(公告)日：2014-03-04
申请号：US13250960
申请日：2011-09-30
IPC分类号： H01L21/02
CPC分类号： H01L21/31116 , H01L21/02057 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process.
摘要翻译： 一种形成半导体器件的方法。 提供了具有第一和第二材料的基板，其中第二材料被第一材料遮挡。 使用第一非等离子体蚀刻工艺蚀刻衬底，相对于蚀刻第二材料的速率，蚀刻第一材料的速率更高。 第一非等离子体蚀刻工艺暴露了覆盖第一材料的至少一部分的第二材料。 然后使用包含暴露第一材料的至少一部分的反应性气体的等离子体来蚀刻第二材料。 使用第二非等离子体蚀刻工艺蚀刻包括通过蚀刻第二材料而暴露的第一材料的至少一部分的第一材料。
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