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    Stacked semiconductor device and method of testing the same
    2.
    发明授权
    Stacked semiconductor device and method of testing the same 有权
    堆叠半导体器件及其测试方法

    公开(公告)号：US08847221B2

    公开(公告)日：2014-09-30

    申请号：US11870550

    申请日：2007-10-11

    申请人： Kayoko Shibata

    发明人： Kayoko Shibata

    IPC分类号： H01L23/58 ,  G01R31/3185 ,  G11C29/02 ,  H01L21/66 ,  H01L23/48 ,  G11C29/50

    CPC分类号： G01R31/318513 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C2029/5006 ,  H01L22/32 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A stacked semiconductor device includes: an internal circuit; a through electrode provided to penetrate through a semiconductor substrate; a test wiring to which a predetermined potential different from a substrate potential is supplied at a time of a test; a first switch arranged between the through electrode and the internal circuit; a second switch arranged between the through electrode and the test wiring; and a control circuit that exclusively turns on the first and the second switches. Thereby, it becomes possible to perform an insulation test in a state that the through electrode and the internal circuit are cut off. Thus, even when a slight short-circuit that does not lead to a current defect occurs, the short circuit can be detected.

    摘要翻译： 叠层半导体器件包括：内部电路; 设置成贯通半导体基板的贯通电极; 在测试时提供与基板电位不同的预定电位的测试布线; 布置在所述通孔电极和所述内部电路之间的第一开关; 布置在所述通孔电极和所述测试布线之间的第二开关; 以及专门打开第一和第二开关的控制电路。 由此，可以在切断贯通电极和内部电路的状态下进行绝缘试验。 因此，即使发生不会导致电流缺陷的轻微短路，也可以检测短路。

    Stacked memory and fuse chip
    4.
    发明授权
    Stacked memory and fuse chip 有权
    堆叠内存和保险丝芯片

    公开(公告)号：US08040745B2

    公开(公告)日：2011-10-18

    申请号：US12392547

    申请日：2009-02-25

    申请人： Kayoko Shibata

    发明人： Kayoko Shibata

    IPC分类号： G11C7/00

    CPC分类号： G11C17/14 ,  G11C5/02 ,  G11C29/006 ,  G11C29/028 ,  G11C29/80 ,  H01L2224/16

    摘要： A stacked memory comprises one or more memory core chips and a fuse chip. Each of the memory core chips has a memory cell array including spare memory cells for replacing defective memory cells. The fuse chip has a fuse unit including a plurality of fuse elements whose electrical cut state corresponding to a replacement with the spare memory cells can be set. Also the fuse chip has a redundancy cell control circuit for controlling a redundancy cell operation of the defective memory cells based on state information of the fuse unit.

    摘要翻译： 堆叠存储器包括一个或多个存储器核心芯片和熔丝芯片。 每个存储核心芯片具有包括用于替换有缺陷的存储器单元的备用存储单元的存储单元阵列。 熔丝芯片具有包括多个熔丝元件的保险丝单元，其中可以设置与替换备用存储单元相对应的电切断状态。 熔丝芯片还具有冗余单元控制电路，用于基于保险丝单元的状态信息来控制有缺陷的存储器单元的冗余单元操作。

    Memory chip and semiconductor device
    5.
    发明申请
    Memory chip and semiconductor device 审中-公开
    内存芯片和半导体器件

    公开(公告)号：US20090303770A1

    公开(公告)日：2009-12-10

    申请号：US12457204

    申请日：2009-06-03

    申请人： Kayoko Shibata

    发明人： Kayoko Shibata

    IPC分类号： G11C5/06 ,  G11C7/10

    CPC分类号： G11C7/18 ,  G11C5/02 ,  G11C5/025 ,  G11C5/063 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2224/0401

    摘要： A memory chip is provided, including internal signal/data terminals disposed in a central part of the memory chip and memory cell arrays arranged around the internal terminals to surround the same and electrically connected thereto. A semiconductor device is also provided, having a memory chip and a logic chip stacked with an interposer interposed therebetween. The logic chip has internal signal/data terminals disposed in its central part and electrically connected to the memory chip. The memory chip includes internal signal/data terminals disposed in its central part, and memory arrays arranged around the internal terminals to surround the same and connected thereto. The internal terminals of the logic chip are connected to the internal terminals of the memory chip via through holes (through electrodes) in the interposer.

    摘要翻译： 提供了一种存储器芯片，包括设置在存储器芯片的中心部分的内部信号/数据端子和围绕内部端子布置以围绕它们并与其电连接的存储单元阵列。 还提供了一种半导体器件，其具有存储器芯片和堆叠在其间插入插入器的逻辑芯片。 逻辑芯片的内部信号/数据端子设置在其中心部分并与存储器芯片电连接。 存储器芯片包括设置在其中心部分的内部信号/数据端子以及围绕内部端子布置以围绕它们并与之连接的存储器阵列。 逻辑芯片的内部端子通过插入器中的通孔（通过电极）连接到存储器芯片的内部端子。

    Memory system, module and register
    7.
    发明授权
    Memory system, module and register 有权
    内存系统，模块和寄存器

    公开(公告)号：US07051225B2

    公开(公告)日：2006-05-23

    申请号：US10427090

    申请日：2003-04-30

    申请人： Yoji Nishio ,  Kayoko Shibata ,  Seiji Funaba

    发明人： Yoji Nishio ,  Kayoko Shibata ,  Seiji Funaba

    IPC分类号： G06F1/04

    CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1093

    摘要： Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAM=1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register. Alternatively, control is made for switching between the replica (replical) provided in the register and an output unit associated with the replica, depending on the frequency being used, so as to cope with both frequencies simply by providing one sort of the module and one sort of the register.

    摘要翻译： 公开了一种存储器命令地址系统和存储器模块，其不仅可以用于266MHzCLK，而且可以用于200MHzCLK，其中PLL，寄存器和DRAM的输入部分中的时钟定时彼此匹配， 在寄存器中提供DLL（延迟锁定环），控制来自寄存器的CA信号的输出定时，使得CA信号的建立时间余量和保持时间裕度相对于时钟信号具有额外的等待时间 DRAM = 1.5或2.0彼此相等，使得例如266MHz的时钟操作成为可能。 如果使用266MHz和200MHz，通过考虑时序预算，进行控制以延迟输入到触发器的CA信号的定时，该触发器接收提供给触发器的内部时钟信号（intCLK） 用于确定来自寄存器的CA信号输出定时。 或者，根据所使用的频率，进行控制以在寄存器中提供的副本（复制）和与副本相关联的输出单元之间进行切换，从而简单地通过提供一种模块和一个模块来处理两个频率 排序的注册表。

    Stacked semiconductor memory device
    8.
    发明申请
    Stacked semiconductor memory device 有权
    堆叠半导体存储器件

    公开(公告)号：US20050286334A1

    公开(公告)日：2005-12-29

    申请号：US11151213

    申请日：2005-06-14

    申请人： Hideaki Saito ,  Yasuhiko Hagihara ,  Muneo Fukaishi ,  Masayuki Mizuno ,  Hiroaki Ikeda ,  Kayoko Shibata

    发明人： Hideaki Saito ,  Yasuhiko Hagihara ,  Muneo Fukaishi ,  Masayuki Mizuno ,  Hiroaki Ikeda ,  Kayoko Shibata

    IPC分类号： G11C5/04 ,  G11C5/06 ,  G11C8/00 ,  H01L25/065

    CPC分类号： G11C5/04 ,  G11C5/063 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/00

    摘要： A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

    摘要翻译： 具有减少在数据传送期间需要充电和放电并因此降低功耗的互连电容的目的的三维半导体存储器件具有：多个存储单元阵列芯片，其中作为分区的子行 组合存储器并且被布置为对应于输入/输出位，堆叠在第一半导体芯片上; 以及用于连接存储单元阵列的芯片间互连，使得子组的相应输入/输出位相同，这些芯片间互连以与输入/输出位数相对应的数量提供并通过存储单元阵列芯片 在堆叠的方向。

    Semiconductor device and testing method of the same
    9.
    发明授权
    Semiconductor device and testing method of the same 有权
    半导体器件及其测试方法相同

    公开(公告)号：US06519726B1

    公开(公告)日：2003-02-11

    申请号：US09461200

    申请日：1999-12-15

    申请人： Kayoko Shibata

    发明人： Kayoko Shibata

    IPC分类号： G11C2900

    CPC分类号： G11C29/40

    摘要： A semiconductor device for testing highly integrated semiconductor devices in a compression mode by using a simple circuit and a specific physical pattern without using address data. The semiconductor device contains memory cell arrays and a device for selecting a test pattern input terminal which selects where a test pattern is to be input from among plural lines selected from bit lines and word lines, and a further device for generating a physical pattern which is constructed so that certain data is inputted in the lines selected to receive the test pattern, and so that the data is simultaneously outputted to data buses connected to plural lines other than the selected lines.

    摘要翻译： 一种用于通过使用简单的电路和特定的物理图案而不使用地址数据来以压缩模式测试高度集成的半导体器件的半导体器件。 半导体器件包括存储单元阵列和用于选择测试图案输入端子的装置，该测试图案输入端子从从位线和字线中选择的多个行中选择要输入测试图案的位置，以及用于产生物理图案的另一设备， 构造成使得某些数据被输入到被选择用于接收测试图案的行中，并且使得数据被同时输出到连接到除所选行以外的多行的数据总线。

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08584061B2

    公开(公告)日：2013-11-12

    申请号：US12923800

    申请日：2010-10-07

    申请人： Kayoko Shibata ,  Hitoshi Miwa ,  Yoshihiko Inoue

    发明人： Kayoko Shibata ,  Hitoshi Miwa ,  Yoshihiko Inoue

    IPC分类号： G06F17/50

    CPC分类号： H01L27/10897 ,  G11C5/063 ,  G11C29/025 ,  G11C29/12 ,  G11C29/1201 ,  H01L22/22 ,  H01L23/481 ,  H01L23/5384 ,  H01L25/0657 ,  H01L27/1052 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01055

    摘要： To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced.

    摘要翻译： 包括包括驱动电路的第一半导体芯片，包括接收电路的第二半导体芯片，以及设置在第二半导体芯片中的硅通孔。 第一半导体芯片包括输出开关电路，其将第i个驱动器电路的输出端（其中i为1至n之间的整数）通过硅通孔中的一个通过硅通孔连接至第（i + m）通过硅通孔。 第二半导体芯片包括输入开关电路，其将第i个接收器电路（其中i是1至n之间的整数）的输入端与第i个至第 + m）通过硅通孔。 利用这种配置，由于在通过硅通孔的替换之前和之后的信号路径之间不发生布线长度的差异，所以可以提高信号质量。