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公开(公告)号：US07687869B2
公开(公告)日：2010-03-30
申请号：US12081824
申请日：2008-04-22
申请人： Akio Kaneko , Seiji Inumiya , Katsuyuki Sekine , Kazuhiro Eguchi , Motoyuki Sato
发明人： Akio Kaneko , Seiji Inumiya , Katsuyuki Sekine , Kazuhiro Eguchi , Motoyuki Sato
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/823842 , H01L21/823857 , H01L29/495 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.
摘要翻译： 根据本发明的半导体器件包括半导体衬底，由主要成分为四价金属氧化物的材料，四价金属氧化物和SiO 2的混合物或四价金属氧化物的混合物构成的栅极绝缘膜 和SiON，并且当其在半导体衬底上处于pMOS结构中时在半导体衬底上为nMOS结构或含有P和As中的至少一种时含有B，并且由具有功函数的金属制成的栅电极 4 eV至5.5 eV。
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公开(公告)号：US20080242115A1
公开(公告)日：2008-10-02
申请号：US11902300
申请日：2007-09-20
IPC分类号： H01L21/31
CPC分类号： H01L29/511 , C23C16/30 , C23C16/45523 , H01L21/28176 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28229 , H01L21/31604 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.
摘要翻译： 一种半导体器件，包括半导体衬底，形成在所述半导体衬底上并包括含有金属元素的氧化硅膜的栅极电介质，所述氧化硅膜含有所述金属元素，所述金属元素包括在其下表面附近的第一区域， 上表面和第一和第二区域之间的第三区域，包含在氧化硅膜中的金属元素在氧化硅膜的厚度方向上具有密度分布，存在于第三区域中的密度分布的峰值， 以及形成在栅极电介质上的电极。
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公开(公告)号：US07282774B2
公开(公告)日：2007-10-16
申请号：US11475879
申请日：2006-06-28
CPC分类号： H01L29/511 , C23C16/30 , C23C16/45523 , H01L21/28176 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28229 , H01L21/31604 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.
摘要翻译： 一种半导体器件，包括半导体衬底，形成在所述半导体衬底上并包括含有金属元素的氧化硅膜的栅极电介质，所述氧化硅膜含有所述金属元素，所述金属元素包括在其下表面附近的第一区域， 上表面和第一和第二区域之间的第三区域，包含在氧化硅膜中的金属元素在氧化硅膜的厚度方向上具有密度分布，存在于第三区域中的密度分布的峰值， 以及形成在栅极电介质上的电极。
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公开(公告)号：US07088291B2
公开(公告)日：2006-08-08
申请号：US11061728
申请日：2005-02-22
IPC分类号： H01Q1/38
摘要： This invention provides an antenna module comprising: a helical antenna 1 including a base 2 and a pair of terminals 4, 5 and a helical area formed on the base 2; a power supply 7 for supplying power to one of the pair of terminals 4, 5 of the helical antenna 1; an opening connected to the other of the pair of terminals; an antenna substrate 9 on which the antenna 7 is mounted; a grounding area 10 formed in the vicinity of the power supply 7; and a peripheral conductor 16 formed at least a portion on the periphery of the antenna substrate 9, wherein the peripheral length of the peripheral conductor 16 formed on the periphery of the antenna substrate 9 is nearly integer times as long as ¼ wavelength of a resonance frequency.
摘要翻译： 本发明提供一种天线模块，包括：螺旋天线1，其包括基座2和一对端子4,5以及形成在基座2上的螺旋区域; 用于向螺旋天线1的一对端子4,5提供电力的电源7; 连接到所述一对端子中的另一个的开口; 安装有天线7的天线基板9; 形成在电源7附近的接地区域10; 以及形成在天线基板9的周围的至少一部分上的外围导体16，其中形成在天线基板9的周围的周边导体16的周长几乎是谐振频率的1/4波长的整数倍 。
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公开(公告)号：US07042418B2
公开(公告)日：2006-05-09
申请号：US10716115
申请日：2003-11-19
申请人： Munenori Fujimura , Hiromi Tokunaga , Shuichiro Yamaguchi , Toshiharu Noguchi , Kazuhiro Eguchi , Kenichi Kozaki , Shigefumi Akagi
发明人： Munenori Fujimura , Hiromi Tokunaga , Shuichiro Yamaguchi , Toshiharu Noguchi , Kazuhiro Eguchi , Kenichi Kozaki , Shigefumi Akagi
IPC分类号： H01Q1/36
摘要： A chip antenna includes a substrate, a plurality of helical conductors provided on the substrate, and a pair of terminals provided on the substrate. One of the plurality of helical conductors is connected electrically to one of the terminals, and another one of the helical conductors is connected electrically to the other terminal. Thus, the antenna is of a small size, yet is a single unit which alone is capable of transmitting and receiving electromagnetic waves of a plurality of frequencies.
摘要翻译： 芯片天线包括基板，设置在基板上的多个螺旋导体和设置在基板上的一对端子。 多个螺旋导体中的一个电连接到一个端子，另一个螺旋导体与另一个端子电连接。 因此，天线尺寸较小，但是单个单元能够发送和接收多个频率的电磁波。
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6.发明申请公开(公告)号：US20050110101A1
公开(公告)日：2005-05-26
申请号：US10927115
申请日：2004-08-27
申请人： Akio Kaneko , Kazuhiro Eguchi , Seiji Inumiya , Katsuyuki Sekine , Motoyuki Sato
发明人： Akio Kaneko , Kazuhiro Eguchi , Seiji Inumiya , Katsuyuki Sekine , Motoyuki Sato
IPC分类号： C23C14/10 , C23C16/42 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L27/04 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/115 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/786 , H01L29/76
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L27/115 , H01L27/1203 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66825 , H01L29/78
摘要： A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.
摘要翻译： 一种半导体装置，其中形成在半导体衬底上的器件包括栅极绝缘膜，该栅极绝缘膜包括形成在基底上的高介电常数膜和形成在高介电常数膜上的抗反应膜，以及形成在抗反应上的栅电极 高介电常数膜包括含有Hf和Zr中的至少一种以及Si和O的膜，或包含Hf和Zr中的至少一种以及Si，O和N的膜，所述抗反应膜包括 SiO 2膜，含有SiO 2作为主要成分的膜和Hf和Zr中的至少一种的膜，含有SiO 2的膜作为 主要成分为N，以SiO 2为主要成分的膜，Hf和N，以SiO 2为主要成分的膜，Zr和N，或膜 含有SiO 2作为主要成分的Hf，Zr和N.
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公开(公告)号：US20050067704A1
公开(公告)日：2005-03-31
申请号：US10738049
申请日：2003-12-18
申请人： Akio Kaneko , Seiji Inumiya , Katsuyuki Sekine , Kazuhiro Eguchi , Motoyuki Sato
发明人： Akio Kaneko , Seiji Inumiya , Katsuyuki Sekine , Kazuhiro Eguchi , Motoyuki Sato
IPC分类号： H01L21/283 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/8238 , H01L23/48 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/823842 , H01L21/823857 , H01L29/495 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.
摘要翻译： 根据本发明的半导体器件包括半导体衬底，由主要成分为四价金属氧化物的材料，四价金属氧化物和SiO 2的混合物或四价金属氧化物的混合物构成的栅极绝缘膜 和SiON，并且当其在半导体衬底上处于pMOS结构中时在半导体衬底上为nMOS结构或含有P和As中的至少一种时含有B，并且由具有功函数的金属制成的栅电极 4 eV至5.5 eV。
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公开(公告)号：US06621378B2
公开(公告)日：2003-09-16
申请号：US09879018
申请日：2001-06-12
申请人： Takumi Naruse , Kuniaki Kiyosue , Hiromi Sakita , Kenzo Isozaki , Kazuhiro Eguchi , Katsumi Sasaki
发明人： Takumi Naruse , Kuniaki Kiyosue , Hiromi Sakita , Kenzo Isozaki , Kazuhiro Eguchi , Katsumi Sasaki
IPC分类号： H03H701
CPC分类号： H03H7/1766 , H03H7/0115 , H03H2001/0085
摘要： A filter includes a substrate with a relative dielectric constant of 200 or less and a thickness of 0.1 mm or more. A first electrode is disposed on at least one surface of the substrate, a group of second electrodes is disposed on at least the other surface of the substrate. Each of the second electrodes is not in contact with each other and is not in contact with the first electrode. The filter also includes a chip type inductance element. The chip type inductance element has an inductance ranging from 0.1 nH to 30 nH and has dimensions of L1 in length, L2 in width and L3 in height, which satisfy the following conditions; 0.3 mm
摘要翻译： 滤波器包括相对介电常数为200以下且厚度为0.1mm以上的基板。 第一电极设置在衬底的至少一个表面上，一组第二电极设置在衬底的至少另一个表面上。 每个第二电极彼此不接触并且不与第一电极接触。 滤波器还包括片式电感元件。 芯片型电感元件的电感范围为0.1 nH〜30 nH，尺寸为L1长度，L2宽，L3高，满足以下条件：
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公开(公告)号：US06326316B1
公开(公告)日：2001-12-04
申请号：US09562330
申请日：2000-05-01
IPC分类号： H01L2131
CPC分类号： H01L28/75 , H01L27/10852 , H01L28/55 , H01L28/91
摘要： Disclosed is a semiconductor device, comprising a semiconductor substrate, a cell transistor formed in the semiconductor substrate, an interlayer dielectric film in which is formed a contact hole communicating with a part of the cell transistor, a contact plug buried in the contact hole formed in the interlayer dielectric film, a capacitor lower electrode formed of a ruthenium/tantalum laminate film consisting of a tantalum film and a ruthenium film formed on the tantalum film, the lower electrode being formed on interlayer dielectric film and connected to the contact plug, a capacitor dielectric film formed on the ruthenium film included in the capacitor lower electrode and consisting of a metal oxide, and a capacitor upper electrode formed on the capacitor dielectric film, the ruthenium film exhibiting (00n) dominant orientation, where n denotes a positive integer.
摘要翻译： 公开了一种半导体器件，包括半导体衬底，形成在半导体衬底中的单元晶体管，层间绝缘膜，其中形成有与单元晶体管的一部分连通的接触孔;埋入在所述接触孔中的接触孔 层间电介质膜，由钽膜和形成在钽膜上的钌膜构成的钌/钽层叠膜形成的电容器下电极，下电极形成在层间绝缘膜上并连接到接触插塞，电容器 在电容器下电极上形成的由金属氧化物构成的钌膜上形成的电介质膜和形成在电容器电介质膜上的电容器上电极，显示（00n）显着取向的钌膜，其中n表示正整数。
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公开(公告)号：US06278152B1
公开(公告)日：2001-08-21
申请号：US09105030
申请日：1998-06-25
IPC分类号： H01L2900
CPC分类号： H01L28/75 , H01L21/76877 , H01L27/10814 , H01L27/10852 , H01L28/55
摘要： A semiconductor device comprises a first lower capacitor electrode composed of a first conductive film, a second lower capacitor electrode composed of a second conductive film which covers at least the side face of the first lower capacitor electrode at its top face, a capacitor insulating film provided on the second lower capacitor electrode, and an upper capacitor electrode provided on the capacitor insulating film, wherein film stress in the first conductive film is lower than that in the second conductive film and the volume of the first conductive film is larger than that of the second conductive film. The above-described structure reduces leakage current in the capacitor.
摘要翻译： 半导体器件包括由第一导电膜构成的第一下电容器电极和由其顶面至少覆盖第一下电容电极的侧面的第二导电膜构成的第二下电容电极，设置有电容器绝缘膜 在第二低电容电极和第二导电膜上设置的上电容器电极，其中第一导电膜中的膜应力低于第二导电膜的膜应力，第一导电膜的体积大于第二导电膜的体积 第二导电膜。 上述结构减小了电容器中的漏电流。
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