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公开(公告)号：US4679188A
公开(公告)日：1987-07-07
申请号：US779639
申请日：1985-09-24
申请人： Misao Fukuda , Toshitaka Tsuda , Kazuo Murano , Yutaka Awata
发明人： Misao Fukuda , Toshitaka Tsuda , Kazuo Murano , Yutaka Awata
CPC分类号： H04L5/1492 , H04L5/1423
摘要： A digital transmission system comprising at least two transmitting-receiving (T/R) units and a single transmission line connected therebetween. One of the T/R units the first transmits a control signal to the other T/R units with which frame synchronization and timing recovery are carried out using the transmitted control signal. At the same time, the other T/R unit inhibits transmission of send signal therefrom to the first T/R unit. Further, the send signal from one T/R unit to the other T/R unit is transmitted in the form of a frame. Each frame includes, at its end portion, a non-signal duration portion.
摘要翻译： 一种包括至少两个发送接收（T / R）单元和连接在它们之间的单个传输线的数字传输系统。 T / R单元之一首先利用这样传输的控制信号将控制信号发送到执行帧同步和定时恢复的其它T / R单元。 同时，另一个T / R单元禁止发送信号到第一T / R单元。 此外，从一个T / R单元到另一个T / R单元的发送信号以帧的形式发送。 每个帧在其端部包括非信号持续时间部分。
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公开(公告)号：US4347617A
公开(公告)日：1982-08-31
申请号：US210850
申请日：1980-11-26
申请人： Kazuo Murano , Kazuo Yamaguchi , Norio Murakami , Toshitaka Tsuda
发明人： Kazuo Murano , Kazuo Yamaguchi , Norio Murakami , Toshitaka Tsuda
CPC分类号： H04L25/4906
摘要： An asynchronous transmission system for binary-coded information is disclosed. According to this system, in a transmitting terminal (A), when successive data of the same code in a set of asynchronous data lasts for a predetermined period of time (T.sub.1), a refresh pulse, the polarity of which is opposite to that of the successive data, is added to a transmission signal. However, the addition of such a refresh pulse to the transmission signal is inhibited for a predetermined period of time (T.sub.2) to allow for a change of data. In a receiving terminal (B), a pulse, the width of which is larger or equal to a minimum period of data, and a pulse, the width of which is smaller than or equal to a pulse-width (T.sub.0) of a refresh pulse, can be discriminated and removed by a pulse-width discrimination circuit. As a result, the refresh pulse is not present in the output signal of the pulse-width discrimination circuit. Thus, the original asynchronous data is restored.
摘要翻译： 公开了一种用于二进制编码信息的异步传输系统。 根据该系统，在发送终端（A）中，当一组异步数据中的相同代码的连续数据持续预定时间段（T1）时，刷新脉冲的极性与 连续数据被添加到传输信号。 然而，在发送信号中添加这样的刷新脉冲在预定时间段（T2）被禁止以允许数据的改变。 在接收终端（B）中，其宽度大于或等于最小数据周期的脉冲，其宽度小于或等于刷新脉冲宽度（T0）的脉冲 脉冲，可以通过脉冲宽度鉴别电路鉴别和去除。 结果，刷新脉冲不存在于脉冲宽度判别电路的输出信号中。 因此，恢复原始异步数据。
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公开(公告)号：US5532822A
公开(公告)日：1996-07-02
申请号：US406171
申请日：1995-03-17
CPC分类号： G03F7/70716
摘要： A method of measuring the orthogonality of a movement coordinate system of a stage unit having a stage which two-dimensionally moves along the movement coordinate system determined by first and second axes that cross each other, by mounting a measurement substrate having at least three measurement patterns on the stage, the at least three measurement patterns including at least two first patterns arranged on a line parallel to a third axis on an array coordinate system determined by the third and fourth axes crossing each other, and at least two second patterns arranged on a line parallel to the fourth axis; aligning the third axis with respect to the first axis of the movement coordinate system; obtaining a difference in an angle between the fourth axis of the array coordinate system and the second axis of the movement coordinate system as a first deviation by detecting the positions of the second patterns on the movement coordinate system in an aligned state; rotating the measurement substrate by 90 degrees from the aligned state and mounting the measurement substrate on the stage; aligning the fourth axis with respect to the first axis of the movement coordinate system; obtaining a difference in an angle between the third axis of the array coordinate system and the second axis of the movement coordinate system as a second deviation by detecting the positions of the first patterns on the movement coordinate system in the aligned state; and obtaining the orthogonality of the movement coordinate system on the basis of the first and second deviations.
摘要翻译： 一种测量具有通过安装具有至少三个测量图案的测量基板沿着彼此交叉的第一和第二轴确定的运动坐标系二维运动的台架的台架单元的运动坐标系的正交性的方法 在舞台上，至少三个测量图案包括布置在由彼此交叉的第三和第四轴确定的阵列坐标系上平行于第三轴线的线上的至少两个第一图案，以及布置在 平行于第四轴线; 相对于移动坐标系的第一轴对准第三轴; 通过在对准状态下检测移动坐标系上的第二图案的位置，获得阵列坐标系的第四轴与移动坐标系的第二轴之间的角度作为第一偏差; 将测量基板从对准状态旋转90度并将测量基板安装在平台上; 使第四轴相对于运动坐标系的第一轴对准; 通过在对准状态下检测移动坐标系上的第一图案的位置，获得阵列坐标系的第三轴与移动坐标系的第二轴之间的角度的差作为第二偏差; 并基于第一和第二偏差获得运动坐标系的正交性。
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4.发明授权Multiplexing apparatus having BSI-code processing and bit interleave functions 失效具有BSI码处理和比特交织功能的多路复用装置
公开(公告)号：US4829518A
公开(公告)日：1989-05-09
申请号：US173540
申请日：1988-03-25
申请人： Kazuo Iquchi , Tetsuo Soejima , Kazuo Murano
发明人： Kazuo Iquchi , Tetsuo Soejima , Kazuo Murano
CPC分类号： H04J3/047 , H04L7/0083
摘要： A multiplexing apparatus of a bit interleave type for time-division multiplex on PCM signals of a plurality of channels bit by bit to convert the PCM signals into a high-speed PCM signal. To maintain the advantage of the synchronous multiplex system, the multiplexing apparatus has a BSI-code processing function and a bit interleave function and comprises: a BSI-code adding circuit for adding BSI codes to the PCM signals before multiplexing; a BSI-code position shifting means circuit for shifting the positions of the BSI codes in the PCM signals to different positions respectively with respect to the PCM signals of a plurality of channels; and a multiplexing circuit for multiplexing the outputs of the BSI-code position shifting circuit by a bit-interleave mode.
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公开(公告)号：US4312075A
公开(公告)日：1982-01-19
申请号：US56641
申请日：1979-07-11
CPC分类号： H04L7/0334 , H04L7/0331
摘要： A timing-phase recovery circuit, which is suitably mounted on a digital LSI, includes a timing phase recovery circuit. The timing-phase recovery circuit includes a first circuit for extracting a digital timing signal from a received input analogue signal, a second circuit for detecting a virtual zero crossing included in the digital timing signal in synchronism with a sampling signal and a third circuit for carrying out a phase shift with respect to the sampling signal in order to tune the timing signal to the frequency of the virtual zero crossings in a very short period of time.
摘要翻译： 适当地安装在数字LSI上的定时相位恢复电路包括定时相位恢复电路。 定时相位恢复电路包括用于从接收到的输入模拟信号中提取数字定时信号的第一电路，用于与采样信号同步地检测包括在数字定时信号中的虚拟过零点的第二电路和用于承载的第三电路 相对于采样信号产生相移，以便在非常短的时间段内将定时信号调谐到虚拟过零点的频率。
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公开(公告)号：US3995218A
公开(公告)日：1976-11-30
申请号：US534878
申请日：1974-12-20
申请人： Takao Moriya , Kazuo Murano
发明人： Takao Moriya , Kazuo Murano
CPC分类号： H03M3/022
摘要： The present invention disclosed an adaptive delta modulation system which examines the several preceding bits of an output of the adaptive delta modulation, and discretely changes a quantizing stepsize of said output so as to compand the same. According to the present invention the system detects the several preceding bits of the output of the adaptive delta modulation, changes the stepsize of that output, counts the output bits of the adaptive delta modulation from the time when stepsize changes, regardless of whether the output is "0" or "1", and changes said stepsize when the counted value reaches a value which is predetermined in accordance with the quantizing stepsize at that time thereby correcting the mistracking which is generated in an adaptation logic circuit between a coder terminal and decoder terminal.
摘要翻译： 本发明公开了一种自适应增量调制系统，该系统检查自适应增量调制的输出的前几个比特，并离散地改变所述输出的量化步长以使其相同。 根据本发明，系统检测自适应增量调制的输出的几个前面的比特，改变该输出的步长，从步长变化的时刻对自适应增量调制的输出比特进行计数，而不管输出是否为 “0”或“1”，并且当计数值达到根据此时的量化步长预定的值时，改变所述步长，从而校正在编码器终端和解码器终端之间的自适应逻辑电路中产生的错误 。
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公开(公告)号：US4975913A
公开(公告)日：1990-12-04
申请号：US250167
申请日：1988-09-28
申请人： Toshiaki Watanabe , Kazuo Murano , Tetsuo Soejima
发明人： Toshiaki Watanabe , Kazuo Murano , Tetsuo Soejima
CPC分类号： H04Q11/0428 , H04J3/1641 , H04L7/0331 , H04J3/0685
摘要： A programmable multiplexing/demultiplexing system used in a digital communication network, suitable for an ISDN to be developed. The system including a phase adjusting unit, a bit length varying unit, a start timing control unit, and a processor which variably controls the three units. The phase adjusting unit variably controls the phase of an internal clock in accordance with received data, and the thus-adjusted clock is used by the remaining two units. The bit length varying unit variably controls the bit length of the received data. The start timing control variably controls the start timing of each transmission and reception processing carried out alternately by the processor.
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公开(公告)号：US4670979A
公开(公告)日：1987-06-09
申请号：US732308
申请日：1985-05-09
申请人： Shigeru Yoshino , Junzo Ueki , Ichiro Shibuya , Shigeo Kawada , Akira Iino , Hiromasa Tanzaki , Kazuo Murano
发明人： Shigeru Yoshino , Junzo Ueki , Ichiro Shibuya , Shigeo Kawada , Akira Iino , Hiromasa Tanzaki , Kazuo Murano
CPC分类号： H05K13/0439 , Y10T29/4914 , Y10T29/53183
摘要： A simplified method of and apparatus for mounting an electronic part such as a transistor on a circuit board. Two or more selected ones of terminals of an electronic part are angularly bent in prior, and when the electronic part is to be mounted on a circuit board, the terminals are forcibly inserted into through-holes of the circuit board to an extent wherein bent portions of the terminals are projected below the circuit board. As a result, if a weak force is applied to pull the part off, the bent portions of the terminals will frictionally engage with edges of the through-holes to prevent the part from being removed from the board.
摘要翻译： 用于将诸如晶体管的电子部件安装在电路板上的简化方法和装置。 电子部件的两个以上选择的端子在以前成角度地弯曲，并且当电子部件被安装在电路板上时，端子被强制地插入到电路板的通孔中，其中弯曲部分 的端子投影在电路板的下方。 结果，如果施加弱力以拉出部件，则端子的弯曲部分将与通孔的边缘摩擦接合，以防止部件从板上移除。
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公开(公告)号：US4920546A
公开(公告)日：1990-04-24
申请号：US176294
申请日：1988-03-31
申请人： Kazuo Iguchi , Tetsuo Soejima , Kazuo Murano , Shigeo Amemiya , Hiroaki Komine , Toshiaki Watanabe , Tomohiro Shinomiya
发明人： Kazuo Iguchi , Tetsuo Soejima , Kazuo Murano , Shigeo Amemiya , Hiroaki Komine , Toshiaki Watanabe , Tomohiro Shinomiya
IPC分类号： H04J3/06
CPC分类号： H04J3/0605
摘要： Disclosed is a frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication. The digital signals consists serial signals at a rate of f.sub.0 (bps). The serial signals include a frame synchronizing signal consituting n bits or a part of the frame synchronizing signal, collectively arranged in one frame. To attain a high-speed operation and a shorter synchronization establishing time, the apparatus comprises a latching circuit for converting the serial signals into parallel signals and for latching the parallel signals, and a circuit for detecting a plural number of times of synchronization during the n bit interval in one frame.
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公开(公告)号：US4788692A
公开(公告)日：1988-11-29
申请号：US876455
申请日：1986-06-20
IPC分类号： H04B14/06
CPC分类号： H04B14/068
摘要： An adaptive differential pulse code modulation system includes an adaptive quantizer and an adaptive predictor which have a coding characteristic optimized to a voice signal, and a quantizer and a predictor which have a coding characteristic optimized to a voice band MODEM signal. This system is normally used as a coding system optimized to the voice signal, and when this system detects a MODEM training signal, it becomes a coding system optimized to the MODEM signal.
摘要翻译： 自适应差分脉码调制系统包括具有针对语音信号优化的编码特性的自适应量化器和自适应预测器，以及具有针对语音频带MODEM信号优化的编码特性的量化器和预测器。 该系统通常用作针对语音信号优化的编码系统，当该系统检测到MODEM训练信号时，它成为针对MODEM信号优化的编码系统。
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