公开(公告)号：US10014315B2

公开(公告)日：2018-07-03

申请号：US15589528

申请日：2017-05-08

申请人： Hyun-suk Kim ,  Joon-hee Lee ,  Kee-jeong Rho

发明人： Hyun-suk Kim ,  Joon-hee Lee ,  Kee-jeong Rho

IPC分类号： H01L27/11573 ,  H01L49/02 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568

CPC分类号： H01L27/11573 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/60 ,  H01L28/91

摘要： Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

公开(公告)号：US09780096B2

公开(公告)日：2017-10-03

申请号：US14965532

申请日：2015-12-10

申请人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L23/528 ,  H01L29/423 ,  H01L29/792 ,  H01L27/108 ,  H01L23/31 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/78 ,  H01L27/1157 ,  H01L27/11575

CPC分类号： H01L27/10897 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US09659954B2

公开(公告)日：2017-05-23

申请号：US14702038

申请日：2015-05-01

申请人： Hyun-suk Kim ,  Joon-hee Lee ,  Kee-jeong Rho

发明人： Hyun-suk Kim ,  Joon-hee Lee ,  Kee-jeong Rho

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L49/02 ,  H01L27/1157 ,  H01L27/11573

CPC分类号： H01L27/11573 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/60 ,  H01L28/91

摘要： Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

公开(公告)号：US20170104000A1

公开(公告)日：2017-04-13

申请号：US15291662

申请日：2016-10-12

申请人： Joo-Hee PARK ,  Jong-Min LEE ,  Seon-Kyung KIM ,  Kee-Jeong RHO ,  Jin-hyun SHIN ,  Jong-Hyun PARK ,  Jin-Yeon WON

发明人： Joo-Hee PARK ,  Jong-Min LEE ,  Seon-Kyung KIM ,  Kee-Jeong RHO ,  Jin-hyun SHIN ,  Jong-Hyun PARK ,  Jin-Yeon WON

IPC分类号： H01L27/115 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

摘要： A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that vertical to a top surface of the substrate, a plurality of gate lines and a conductive line on the substrate. The gate lines are stacked on top of each other. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction. The conductive line cuts the gate lines along the first direction. A width of the conductive line is periodically and repeatedly changed.

公开(公告)号：US20170243878A1

公开(公告)日：2017-08-24

申请号：US15589528

申请日：2017-05-08

申请人： Hyun-suk KIM ,  Joon-hee LEE ,  Kee-jeong RHO

发明人： Hyun-suk KIM ,  Joon-hee LEE ,  Kee-jeong RHO

IPC分类号： H01L27/11573 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11521 ,  H01L49/02

CPC分类号： H01L27/11573 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/60 ,  H01L28/91

摘要： Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

公开(公告)号：US20150318296A1

公开(公告)日：2015-11-05

申请号：US14702038

申请日：2015-05-01

申请人： Hyun-suk Kim ,  Joon-hee Lee ,  Kee-jeong Rho

发明人： Hyun-suk Kim ,  Joon-hee Lee ,  Kee-jeong Rho

IPC分类号： H01L27/115 ,  H01L49/02

CPC分类号： H01L27/11573 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/60 ,  H01L28/91

摘要： Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

摘要翻译： 提供了一种垂直非易失性存储器件，其中构成外围电路区域的电容器形成为垂直型，使得与平面电容器相比，整个器件中的电容器占据的面积可以减小。 因此，非易失性存储器件可以高度集成并具有高容量。 该装置包括具有单元区域和外围电路区域的基板，包括形成在单元区域中的多个垂直存储单元的存储单元串和形成为沿垂直于基板的第一方向穿透垂直存储单元的通道孔， 形成在基板上的外围电路区域中的与存储单元串的上表面基本相同的绝缘层，以及形成在外围电路区域上的多个电容器电极，以穿透绝缘层的至少一部分 第一方向，多个电容器电极平行于通道孔延伸。 多个电容器电极在与基板平行的第二方向上彼此间隔开，并且绝缘层插入在多个电容器电极中的一对相邻的电容器电极之间。

公开(公告)号：US10811421B2

公开(公告)日：2020-10-20

申请号：US15712836

申请日：2017-09-22

申请人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L27/108 ,  H01L27/1157 ,  H01L27/11575 ,  H01L23/31 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US20180026041A1

公开(公告)日：2018-01-25

申请号：US15712836

申请日：2017-09-22

申请人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L27/108 ,  H01L29/792 ,  H01L29/78 ,  H01L29/423 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/1157 ,  H01L23/31 ,  H01L27/11582

CPC分类号： H01L27/10897 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US20160204111A1

公开(公告)日：2016-07-14

申请号：US14965532

申请日：2015-12-10

申请人： Sang-Yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-Yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L27/108 ,  H01L29/78 ,  H01L23/31 ,  H01L23/528 ,  H01L29/423 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L27/10897 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

摘要翻译： 垂直存储器件及其制造方法包括提供包括电池阵列区域和外围电路区域的衬底，在电池阵列区域中形成模具结构，形成通过模具结构的共同源极线的开口，以及 在垂直于衬底的顶表面的第一方向上延伸，形成第一接触插塞，该第一接触插塞具有限定用于公共源极线的开口中的凹陷区域的内侧壁，以及形成与内侧壁电连接的公共源位线接触 的第一个接触插头。