公开(公告)号：US06869840B2

公开(公告)日：2005-03-22

申请号：US10645399

申请日：2003-08-21

Applicant: Amitava Chatterjee ,  Keith E. Kunz

Inventor： Amitava Chatterjee ,  Keith E. Kunz

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L23/62 ,  H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrostatic discharge (ESD) protection structures utilizing bipolar conduction are disclosed. The structures each include a parasitic p-n-p bipolar transistor (102); some of the disclosed embodiments include this transistor within a silicon-controlled-rectifier (SCR) type of ESD protection structure. A p+ doped region (116, 216, 316, 416, 516) is disposed at a surface of an n-well (112, 212, 312, 412, 512) overlying a location (115, 215, 315, 415, 515) that receives both the n-well (112, 212, 312, 412, 512) implants and also the p-well (213, 313, 413, 513) implants. Preferably, the well implants are designed to provide retrograde doping profiles. The number of net impurities is reduced, and thus the base Gummel number is lowered, at the compensated well portion (112′, 212′, 312′, 412′, 512′), resulting in improved gain for the vertical bipolar device.

Abstract translation: 公开了利用双极导电的静电放电（ESD）保护结构。 所述结构各自包括寄生p-n-p双极晶体管（102）; 一些所公开的实施例包括在硅控整流器（SCR）类型的ESD保护结构内的该晶体管。 p +掺杂区域（116,216,316,416,516）设置在覆盖位置（115,215,315,415,515）上的n阱（112,212,312,412,512）的表面上， 其接收n阱（112,212,312,412,512）植入物以及p阱（213,313,413,513）植入物。 优选地，井注入被设计成提供逆向掺杂分布。 在补偿的井部分（112'，212'，312'，412'，512'），净杂质的数量减少，从而碱基Gummel数降低，导致垂直双极器件的增益增加。

公开(公告)号：US06836148B2

公开(公告)日：2004-12-28

申请号：US10141297

申请日：2002-05-08

Applicant: Donald T. Pullen ,  Norman L. Culp ,  Xiaoyu Xi ,  Keith E. Kunz

Inventor： Donald T. Pullen ,  Norman L. Culp ,  Xiaoyu Xi ,  Keith E. Kunz

IPC: H03K190185

CPC classification number: H03K19/00315

Abstract: A output driver architecture (100) is proposed that uses thin gate-oxide core and thin gate-oxide Drain-extended transistors that can directly interface with voltage supplies up to six times the normal rating of the transistor. A bias generator (101), level shifter (103) and output stage (105) are adapted to buffer an input signal with a voltage swing of less than the normal operating voltage of the transistors to an output signal with a voltage swing of up to approximately six times the normal operating voltage of the transistors. The bias generator is interfaced directly with a high voltage power supply and generates a bias voltage with a magnitude of less than the dielectric breakdown of the transistors internal to the level shifter and output stage. Further, the bias generator is adapted to sense the magnitude of the high voltage supply, and to automatically and continuously self-adjust the bias voltage in response to changes sensed in the magnitude of the high voltage supply such that the bias generator can be used for a continuous range of high voltage supplies up to 6 times the normal operating voltage of the transistors.

Abstract translation: 提出了一种输出驱动器架构（100），其使用薄栅极氧化物核和薄栅极氧化物漏极扩展晶体管，其可以直接与高达晶体管正常额定值的六倍的电压源接口。 偏置发生器（101），电平移位器（103）和输出级（105）适于将具有小于晶体管的正常工作电压的电压摆幅的输入信号缓冲到具有高达 大约是晶体管正常工作电压的六倍。 偏置发生器直接与高压电源接口，并产生一个小于电平转换器和输出级内部晶体管的介质击穿电压的偏置电压。 此外，偏置发生器适于感测高压电源的大小，并且响应于在高压电源的幅度中感测到的变化而自动且连续地自适应偏置电压，使得偏置发生器可用于 连续的高压电源范围高达晶体管正常工作电压的6倍。

公开(公告)号：US06639284B1

公开(公告)日：2003-10-28

申请号：US10280829

申请日：2002-10-25

Applicant: Amitava Chatterjee ,  Keith E. Kunz

Inventor： Amitava Chatterjee ,  Keith E. Kunz

IPC: H01L2362

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrostatic discharge (ESD) protection structures utilizing bipolar conduction are disclosed. The structures each include a parasitic p-n-p bipolar transistor (102); some of the disclosed embodiments include this transistor within a silicon-controlled-rectifier (SCR) type of ESD protection structure. A p+ doped region (116, 216, 316, 416, 516) is disposed at a surface of an n-well (112, 212, 312, 412, 512) overlying a location (115, 215, 315, 415, 515) that receives both the n-well (112, 212, 312, 412, 512) implants and also the p-well (213, 313, 413, 513) implants. Preferably, the well implants are designed to provide retrograde doping profiles. The number of net impurities is reduced, and thus the base Gummel number is lowered, at the compensated well portion (112′, 212′, 312′, 412′, 512′), resulting in improved gain for the vertical bipolar device.

Abstract translation: 公开了利用双极导电的静电放电（ESD）保护结构。 所述结构各自包括寄生p-n-p双极晶体管（102）; 一些所公开的实施例包括在硅控整流器（SCR）类型的ESD保护结构内的该晶体管。 p +掺杂区域（116,216,316,416,516）设置在覆盖位置（115,215,315,415,515）上的n阱（112,212,312,412,512）的表面上， 其接收n阱（112,212,312,412,512）植入物以及p阱（213,313,413,513）植入物。 优选地，井注入被设计成提供逆向掺杂分布。 在补偿的井部分（112'，212'，312'，412'，512'），净杂质的数量减少，从而碱基Gummel数降低，导致垂直双极器件的增益增加。

公开(公告)号：US06576959B2

公开(公告)日：2003-06-10

申请号：US09947272

申请日：2001-09-05

Applicant: Keith E. Kunz ,  Charvaka Duvvury ,  Hisashi Shichijo

Inventor： Keith E. Kunz ,  Charvaka Duvvury ,  Hisashi Shichijo

IPC: H01L2362

CPC classification number: H01L27/0262

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

公开(公告)号：US07768351B2

公开(公告)日：2010-08-03

申请号：US12215186

申请日：2008-06-25

Applicant: Vadim V. Ivanov ,  Keith E. Kunz ,  Sachin Rao Bandigadi ,  Prasadu Naga Venkata Mangina

Inventor： Vadim V. Ivanov ,  Keith E. Kunz ,  Sachin Rao Bandigadi ,  Prasadu Naga Venkata Mangina

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F3/45179 ,  H03F2203/45674

Abstract: Variable gain circuitry includes a first input transistor (M1) having a source coupled to a first conductor (32), a gate coupled to a first input voltage (Vin+), and a drain coupled to a second conductor (30). An input of a first current mirror (M3,M4) is coupled to the second conductor to receive a current corresponding to the difference between the first input voltage and a second input voltage (Vin−). An output of the first current mirror is coupled to a source of current (M2). A first transistor (M5) has a gate coupled to a third conductor (31), a source coupled to a reference voltage (VSS), and a drain coupled to conduct output current (Iout). A second transistor (M6) and a resistive element (M7) are coupled in series between the third conductor and the first reference voltage (VSS), a gate of the second transistor being coupled to the third conductor to produce a nonlinear relationship between currents of the first transistor and the second transistor.

Abstract translation: 可变增益电路包括具有耦合到第一导体（32）的源极的第一输入晶体管（M1），耦合到第一输入电压（Vin +）的栅极和耦合到第二导体（30）的漏极。 第一电流镜（M3，M4）的输入耦合到第二导体，以接收对应于第一输入电压和第二输入电压（Vin-）之间的差的电流。 第一电流镜的输出耦合到电流源（M2）。 第一晶体管（M5）具有耦合到第三导体（31）的栅极，耦合到参考电压（VSS）的源极和耦合以导通输出电流（Iout）的漏极。 第二晶体管（M6）和电阻元件（M7）串联耦合在第三导体和第一参考电压（VSS）之间，第二晶体管的栅极耦合到第三导体，以产生电流之间的非线性关系 第一晶体管和第二晶体管。

公开(公告)号：US20090179622A1

公开(公告)日：2009-07-16

申请号：US12008533

申请日：2008-01-11

Applicant: Vadim V. Ivanov ,  Keith E. Kunz

Inventor： Vadim V. Ivanov ,  Keith E. Kunz

IPC: G05F1/08

CPC classification number: G05F1/575

Abstract: An LDO regulator (10) produces an output voltage (Vout) by applying the output voltage to a feedback input (6) of a differential input stage (10A) and applying an output (3) of the differential input stage to a gate of a first follower transistor (MP4) having a source coupled to an input (8) of a class AB output stage (10C) which generates the output voltage. Demanded load current is supplied by the output voltage during a dip in its value to a gate of a second follower transistor (MP5) having a gate coupled to the output of the input stage to decrease current in a current mirror (MN5,6) having an output coupled to a current source (I1) and a gate of an amplifying transistor (MN7). This causes the current source to rapidly turn on the amplifying transistor to cause it to rapidly turn on a cascode transistor (MN3), causing it to turn on a pass transistor (MP3) of the output stage.

公开(公告)号：US06804095B2

公开(公告)日：2004-10-12

申请号：US10618893

申请日：2003-07-14

Applicant: Keith E. Kunz ,  Charvaka Duvvury ,  Dan M. Mosher

Inventor： Keith E. Kunz ,  Charvaka Duvvury ,  Dan M. Mosher

IPC: H02H900

CPC classification number: H01L27/0266

Abstract: A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed. An ESD event received at the terminal (IN) is thus coupled to the gate of the transistors (32, 34), causing conduction to the substrate (40) via the guard ring (50), and turning on a parasitic bipolar transistor at the other transistor (34), safely conducting the ESD current. One alternative structure (30′) includes a junction capacitor (65) coupled between the terminal (IN) and the gates of the transistors (32, 34) to improve the coupling. Another alternative structure (30″) includes a clamping diode (92) that also presents a parasitic bipolar transistor (95) enhancing the current conducted to the substrate (40).

Abstract translation: 公开了一种用于在端子（IN）处安全地从静电放电（ESD）传导电荷的保护结构（30; 30'; 30“）。 保护结构（30; 30'; 30“）包括一对漏极延伸的金属氧化物半导体（MOS）晶体管（32,34）。 在泵浦晶体管（32）中，栅电极（45）与布置有漏极（44）的阱（42）的一部分重叠，以提供有效的栅 - 漏电容。 晶体管（32,34）的漏极连接在一起并连接到端子（IN），而晶体管（32,34）的栅极连接在一起。 一个晶体管（32）的源极连接到与其他晶体管（34）的沟道区域设置在其中的衬底（40）相同的导电类型的保护环（50）。 因此，在端子（IN）处接收到的ESD事件被耦合到晶体管（32,34）的栅极，从而经由保护环（50）导通到衬底（40），并且在第 其他晶体管（34），安全地传导ESD电流。 一个替代结构（30'）包括耦合在端子（IN）和晶体管（32,34）的栅极之间的结电容器（65），以改善耦合。 另一替代结构（30“）包括钳位二极管（92），其还具有增强传导到衬底（40）的电流的寄生双极晶体管（95）。

公开(公告)号：US08159207B2

公开(公告)日：2012-04-17

申请号：US12610944

申请日：2009-11-02

Applicant: Vadim V. Ivanov ,  Keith E. Kunz

Inventor： Vadim V. Ivanov ,  Keith E. Kunz

IPC: G05F3/16

CPC classification number: G05F1/575

Abstract: An LDO regulator (10) produces an output voltage (Vout) by applying the output voltage to a feedback input (6) of a differential input stage (10A) and applying an output (3) of the differential input stage to a gate of a first follower transistor (MP4) having a source coupled to an input (8) of a class AB output stage (10C) which generates the output voltage. Demanded load current is supplied by the output voltage during a dip in its value to a gate of a second follower transistor (MP5) having a gate coupled to the output of the input stage to decrease current in a current mirror (MN5,6) having an output coupled to a current source (I1) and a gate of an amplifying transistor (MN7). This causes the current source to rapidly turn on the amplifying transistor to cause it to rapidly turn on a cascode transistor (MN3), causing it to turn on a pass transistor (MP3) of the output stage.

Abstract translation: LDO调节器（10）通过将输出电压施加到差分输入级（10A）的反馈输入（6）并且将差分输入级的输出（3）施加到一个门极，产生输出电压（Vout） 第一跟随器晶体管（MP4）具有耦合到产生输出电压的AB类输出级（10C）的输入端（8）的源极。 所需负载电流在其下降期间的输出电压被提供给具有耦合到输入级的输出端的栅极的第二跟随器晶体管（MP5）的栅极，以减少电流镜（MN5,6）中的电流， 耦合到电流源（I1）和放大晶体管（MN7）的栅极的输出。 这使得电流源快速地导通放大晶体管，使其迅速接通共源共栅晶体管（MN3），使其导通输出级的传输晶体管（MP3）。

公开(公告)号：US20100045380A1

公开(公告)日：2010-02-25

申请号：US12610944

申请日：2009-11-02

Applicant: Vadim V. Ivanov ,  Keith E. Kunz

Inventor： Vadim V. Ivanov ,  Keith E. Kunz

IPC: H03F3/45

CPC classification number: G05F1/575

Abstract: An LDO regulator (10) produces an output voltage (Vout) by applying the output voltage to a feedback input (6) of a differential input stage (10A) and applying an output (3) of the differential input stage to a gate of a first follower transistor (MP4) having a source coupled to an input (8) of a class AB output stage (10C) which generates the output voltage. Demanded load current is supplied by the output voltage during a dip in its value to a gate of a second follower transistor (MP5) having a gate coupled to the output of the input stage to decrease current in a current mirror (MN5,6) having an output coupled to a current source (I1) and a gate of an amplifying transistor (MN7). This causes the current source to rapidly turn on the amplifying transistor to cause it to rapidly turn on a cascode transistor (MN3), causing it to turn on a pass transistor (MP3) of the output stage.

Abstract translation: LDO调节器（10）通过将输出电压施加到差分输入级（10A）的反馈输入（6）并且将差分输入级的输出（3）施加到一个门极，产生输出电压（Vout） 第一跟随器晶体管（MP4）具有耦合到产生输出电压的AB类输出级（10C）的输入端（8）的源极。 所需负载电流在其下降期间的输出电压被提供给具有耦合到输入级的输出端的栅极的第二跟随器晶体管（MP5）的栅极，以减少电流镜（MN5,6）中的电流， 耦合到电流源（I1）和放大晶体管（MN7）的栅极的输出。 这使得电流源快速地导通放大晶体管，使其迅速接通共源共栅晶体管（MN3），使其导通输出级的传输晶体管（MP3）。

公开(公告)号：US06764892B2

公开(公告)日：2004-07-20

申请号：US10445743

申请日：2003-05-27

Applicant: Keith E. Kunz ,  Charvaka Duvvury ,  Hisashi Shichijo

Inventor： Keith E. Kunz ,  Charvaka Duvvury ,  Hisashi Shichijo

IPC: H01L218238

CPC classification number: H01L27/0262 ,  H01L29/87

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract translation: 描述了具有内置静电放电（ESD）保护的多电压操作的半导体电路，包括与晶体管合并的漏极扩展nMOS晶体管和pnpn可控硅整流器（SCR），从而产生双重npn结构， 晶体管的源极和SCR的阴极连接到电接地电位，形成双阴极，从而增强了ESD保护。 整流器具有形成突起结的扩散区，电阻耦合到漏极，由此可以在nMOS晶体管漏极击穿之前触发SCR的电击穿到衬底。 SCR具有由半导体表面区域隔开的阳极和阴极区域，并且位于表面区域上方的绝缘层具有适合于高电压操作和ESD保护的厚度。