公开(公告)号：US20050191828A1

公开(公告)日：2005-09-01

申请号：US11003000

申请日：2004-12-01

申请人： Amir Al-Bayati ,  Rick Roberts ,  Kenneth Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

发明人： Amir Al-Bayati ,  Rick Roberts ,  Kenneth Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

IPC分类号： H01J37/32 ,  H01L21/4763

CPC分类号： H01J37/32082 ,  H01J37/321 ,  H01L21/76254

摘要： An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielectric material with plural gas bubbles distributed within the volume of the dielectric material to reduce the dielectric constant of the material, the gas bubbles being formed by ion implantation of a gaseous species into the dielectric material.

摘要翻译： 集成的微电子电路具有覆盖由堆叠的金属图案层和分离相邻的所述金属图案层的绝缘层的晶体管的多层互连结构。 每个绝缘层是具有分布在电介质材料的体积内的多个气泡的介电材料，以降低材料的介电常数，气泡通过将气态物质离子注入电介质材料而形成。

公开(公告)号：US20050266622A1

公开(公告)日：2005-12-01

申请号：US10854013

申请日：2004-05-25

申请人： Reza Arghavani ,  Ken MacWilliams ,  Hichem M'Saad

发明人： Reza Arghavani ,  Ken MacWilliams ,  Hichem M'Saad

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/336 ,  H01L21/44 ,  H01L21/8234

CPC分类号： H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185

摘要： A method of forming a sidewall spacer on a gate electrode of a metal oxide semiconductor device that includes striking a first plasma to form an oxide layer on a side of the gate electrode, where the first plasma is generated from a oxide gas that includes O3 and bis-(tertiarybutylamine)silane, and striking a second plasma to form a carbon-doped nitride layer on the oxide layer, where the second plasma may be generated from a nitride gas that includes NH3 and the bis-(tertiarybutylamine)silane. The first and second plasmas may be formed using plasma CVD and the bis-(tertiarybutylamine)silane flows uninterrupted between the striking of the first plasma and the striking of the second plasma.

摘要翻译： 一种在金属氧化物半导体器件的栅电极上形成侧壁间隔物的方法，其包括冲击第一等离子体以在栅电极的一侧上形成氧化物层，其中第一等离子体由氧化物气体产生， 和三（叔丁基胺）硅烷，并且冲击第二等离子体以在氧化物层上形成碳掺杂的氮化物层，其中第二等离子体可以由氮化物气体产生， 3和双 - （叔丁胺）硅烷。 可以使用等离子体CVD形成第一和第二等离子体，并且双（叔丁胺）硅烷在第一等离子体的击打和第二等离子体的击打之间不间断地流动。

公开(公告)号：US07166524B2

公开(公告)日：2007-01-23

申请号：US11003000

申请日：2004-12-01

申请人： Amir Al-Bayati ,  Rick J. Roberts ,  Kenneth S. Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

发明人： Amir Al-Bayati ,  Rick J. Roberts ,  Kenneth S. Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

IPC分类号： H01L21/425

CPC分类号： H01J37/32082 ,  H01J37/321 ,  H01L21/76254

摘要： An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielectric material with plural gas bubbles distributed within the volume of the dielectric material to reduce the dielectric constant of the material, the gas bubbles being formed by ion implantation of a gaseous species into the dielectric material.

摘要翻译： 集成的微电子电路具有覆盖由堆叠的金属图案层和分离相邻的所述金属图案层的绝缘层的晶体管的多层互连结构。 每个绝缘层是具有分布在电介质材料的体积内的多个气泡的介电材料，以降低材料的介电常数，气泡通过将气态物质离子注入电介质材料而形成。

公开(公告)号：US20070042580A1

公开(公告)日：2007-02-22

申请号：US11551196

申请日：2006-10-19

申请人： Amir Al-Bayati ,  Rick Roberts ,  Kenneth Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

发明人： Amir Al-Bayati ,  Rick Roberts ,  Kenneth Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

IPC分类号： H01L21/425

CPC分类号： H01L21/823864 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/823871 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielectric material with plural gas bubbles distributed within the volume of the dielectric material to reduce the dielectric constant of the material, the gas bubbles being formed by ion implantation of a gaseous species into the dielectric material.

摘要翻译： 集成的微电子电路具有覆盖由堆叠的金属图案层和分离相邻的所述金属图案层的绝缘层的晶体管的多层互连结构。 每个绝缘层是具有分布在电介质材料的体积内的多个气泡的介电材料，以降低材料的介电常数，气泡通过将气态物质离子注入电介质材料而形成。

公开(公告)号：US07049200B2

公开(公告)日：2006-05-23

申请号：US10854013

申请日：2004-05-25

申请人： Reza Arghavani ,  Ken MacWilliams ,  Hichem M'Saad

发明人： Reza Arghavani ,  Ken MacWilliams ,  Hichem M'Saad

IPC分类号： H01L21/336

CPC分类号： H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185

摘要： A method of forming a sidewall spacer on a gate electrode of a metal oxide semiconductor device that includes striking a first plasma to form an oxide layer on a side of the gate electrode, where the first plasma is generated from a oxide gas that includes O3 and bis-(tertiarybutylamine)silane, and striking a second plasma to form a carbon-doped nitride layer on the oxide layer, where the second plasma may be generated from a nitride gas that includes NH3 and the bis-(tertiarybutylamine)silane. The first and second plasmas may be formed using plasma CVD and the bis-(tertiarybutylamine)silane flows uninterrupted between the striking of the first plasma and the striking of the second plasma.

摘要翻译： 一种在金属氧化物半导体器件的栅电极上形成侧壁间隔物的方法，其包括冲击第一等离子体以在栅电极的一侧上形成氧化物层，其中第一等离子体由氧化物气体产生， 和三（叔丁基胺）硅烷，并且冲击第二等离子体以在氧化物层上形成碳掺杂的氮化物层，其中第二等离子体可以由氮化物气体产生， 3和双 - （叔丁胺）硅烷。 可以使用等离子体CVD形成第一和第二等离子体，并且双（叔丁胺）硅烷在第一等离子体的击打和第二等离子体的击打之间不间断地流动。