公开(公告)号：US20090014790A1

公开(公告)日：2009-01-15

申请号：US12167764

申请日：2008-07-03

申请人： Seiji OTAKE ,  Yasuhiro TAKEDA ,  Kenichi MAKI

发明人： Seiji OTAKE ,  Yasuhiro TAKEDA ,  Kenichi MAKI

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7809

摘要： A semiconductor device includes a gate electrode formed through an insulating film in a groove having a first side surface adjacent to a source region and a base region, and a second conductive type first impurity region formed adjacent to a second side surface of the groove between the groove and a lead-out portion of a drain region existing below the base region so as to extend downward beyond a lower end of the groove.

摘要翻译： 一种半导体器件包括：栅极，其形成在沟槽中，绝缘膜具有与源极区域和基极区域相邻的第一侧面;以及第二导电型第一杂质区域，其形成在所述沟槽的第二侧面附近， 凹槽和存在于底部区域下方的漏区的引出部分，以便向下延伸超过凹槽的下端。

公开(公告)号：US07768067B2

公开(公告)日：2010-08-03

申请号：US12425592

申请日：2009-04-17

申请人： Seiji Otake ,  Shuichi Kikuchi ,  Yasuhiro Takeda ,  Kenichi Maki

发明人： Seiji Otake ,  Shuichi Kikuchi ,  Yasuhiro Takeda ,  Kenichi Maki

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7816 ,  H01L29/0878 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66689

摘要： This invention provides a DMOS transistor that has a reduced ON resistance and is prevented from deterioration in strength against an electrostatic discharge. An edge portion of a source layer of the DMOS transistor is disposed so as to recede from an inner corner portion of a gate electrode. A silicide layer is structured so as not to extend out of the edge portion of the source layer. That is, although the silicide layer is formed on a surface of the source layer, the silicide layer is not formed on a surface of a portion of a body layer, which is exposed between the source layer and the inner corner portion of the gate electrode. As a result, the strength against the electrostatic discharge can be improved, because an electric current flows almost uniformly through whole of the DMOS transistor without converging.

摘要翻译： 本发明提供一种DMOS晶体管，其具有降低的导通电阻并且防止其相对静电放电的强度劣化。 DMOS晶体管的源极层的边缘部分被设置为从栅电极的内角部分退出。 硅化物层被构造为不从源极层的边缘部分延伸出来。 也就是说，尽管在源极层的表面上形成硅化物层，但是在源极层和栅电极的内角部之间露出的体层的一部分的表面上不形成硅化物层 。 结果，由于电流几乎均匀地流过整个DMOS晶体管而没有会聚，所以可以提高抵抗静电放电的强度。

公开(公告)号：US20090261410A1

公开(公告)日：2009-10-22

申请号：US12425592

申请日：2009-04-17

申请人： Seiji OTAKE ,  Shuichi Kikuchi ,  Yasuhiro Takeda ,  Kenichi Maki

发明人： Seiji OTAKE ,  Shuichi Kikuchi ,  Yasuhiro Takeda ,  Kenichi Maki

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0878 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66689

摘要： This invention provides a DMOS transistor that has a reduced ON resistance and is prevented from deterioration in strength against an electrostatic discharge. An edge portion of a source layer of the DMOS transistor is disposed so as to recede from an inner corner portion of a gate electrode. A silicide layer is structured so as not to extend out of the edge portion of the source layer. That is, although the silicide layer is formed on a surface of the source layer, the silicide layer is not formed on a surface of a portion of a body layer, which is exposed between the source layer and the inner corner portion of the gate electrode. As a result, the strength against the electrostatic discharge can be improved, because an electric current flows almost uniformly through whole of the DMOS transistor without converging.

摘要翻译： 本发明提供一种DMOS晶体管，其具有降低的导通电阻并且防止其相对静电放电的强度劣化。 DMOS晶体管的源极层的边缘部分被设置为从栅电极的内角部分退出。 硅化物层被构造为不从源极层的边缘部分延伸出来。 也就是说，尽管在源极层的表面上形成硅化物层，但是在源极层和栅电极的内角部之间露出的体层的一部分的表面上不形成硅化物层 。 结果，由于电流几乎均匀地流过整个DMOS晶体管而没有会聚，所以可以提高抵抗静电放电的强度。

公开(公告)号：US5572977A

公开(公告)日：1996-11-12

申请号：US293460

申请日：1994-08-22

申请人： Hiroshi Shibata ,  Yoichi Nishiyori ,  Kenichi Maki ,  Hiroshi Kondo

发明人： Hiroshi Shibata ,  Yoichi Nishiyori ,  Kenichi Maki ,  Hiroshi Kondo

IPC分类号： F02D41/10 ,  F02D41/34 ,  F02D45/00 ,  F02D41/26

CPC分类号： F02D41/34 ,  F02D41/105 ,  Y02T10/44

摘要： A fuel injection control system having an intelligent timer (TPU) to perform fuel injection control using the TPU even on request of asynchronous injection which is not synchronous with rotational angle signals. A central processing unit (CPU) calculates a value to be used during the execution of a synchronous injection (e.g., a fuel injection time) and an asynchronous injection time and stores these values in a parameter RAM. The CPU determines whether there is a request for an asynchronous injection from, for example, the quantity of a change in the opening of a throttle. The TPU also executes a synchronous injection if there is no asynchronous injection request. If there is an asynchronous injection request, it transmits an on output from input/output pins and causes a compare register to store a value which is the sum of the current time and an asynchronous injection time. It transmits an off output from the input/output pins if this value agrees with a value in a first free run counter.

摘要翻译： 一种具有智能定时器（TPU）的燃料喷射控制系统，即使在与旋转角度信号不同步的异步喷射的请求下也使用TPU执行燃料喷射控制。 中央处理单元（CPU）计算在执行同步喷射（例如燃料喷射时间）和异步喷射时间期间要使用的值，并将这些值存储在参数RAM中。 CPU从例如节气门开度的变化量确定是否存在异步喷射的请求。 如果没有异步注入请求，TPU也会执行同步注入。 如果有异步注入请求，它会从输入/输出引脚发送一个输出，并使比较寄存器存储一个值，该值是当前时间和异步注入时间之和。 如果该值与第一个自由运行计数器中的值一致，则它从输入/输出引脚发送关断输出。

公开(公告)号：US07948031B2

公开(公告)日：2011-05-24

申请号：US12167764

申请日：2008-07-03

申请人： Seiji Otake ,  Yasuhiro Takeda ,  Kenichi Maki

发明人： Seiji Otake ,  Yasuhiro Takeda ,  Kenichi Maki

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7809

摘要： A semiconductor device includes a gate electrode formed through an insulating film in a groove having a first side surface adjacent to a source region and a base region, and a second conductive type first impurity region formed adjacent to a second side surface of the groove between the groove and a lead-out portion of a drain region existing below the base region so as to extend downward beyond a lower end of the groove.

摘要翻译： 一种半导体器件包括：栅极，其形成在沟槽中，绝缘膜具有与源极区域和基极区域相邻的第一侧面;以及第二导电型第一杂质区域，其形成在所述沟槽的第二侧面附近， 凹槽和存在于基底区域下方的漏区的引出部分，以便向下延伸超过凹槽的下端。

公开(公告)号：US06199002B1

公开(公告)日：2001-03-06

申请号：US09198393

申请日：1998-11-24

申请人： Tetsuya Otaki ,  Kenichi Maki ,  Masaya Oi ,  Koji Nagata

发明人： Tetsuya Otaki ,  Kenichi Maki ,  Masaya Oi ,  Koji Nagata

IPC分类号： G06F1700

CPC分类号： G05B13/024 ,  B60G2600/02 ,  B60G2600/09 ,  B60G2600/1877 ,  B60G2800/70 ,  G05B5/01 ,  G05B11/28

摘要： A control method and apparatus which detects a solenoid current as a voltage, and PWM-controls a transistor for a solenoid such that the detection voltage becomes a target voltage. A feedback gain, used for setting PWM signal output time, is set in accordance with the difference between the detection voltage and the target voltage such that the greater the difference becomes, the greater the feedback gain becomes. Further, a detection voltage after a predetermined period is estimated based on the change of detection voltage from the past. If the estimation value overshoots the target voltage, a difference B between the detection voltage and the target voltage and a difference C between the detection voltage and the estimation value are obtained, and the feedback gain is varied by multiplying the feedback gain by the ratio B/C between the these differences.

摘要翻译： 一种将螺线管电流检测为电压的控制方法和装置，并且PWM控制螺线管的晶体管，使得检测电压成为目标电压。 用于设置PWM信号输出时间的反馈增益根据检测电压和目标电压之间的差设定，使得差越大，反馈增益越大。 此外，基于过去的检测电压的变化来估计预定时段之后的检测电压。 如果估计值超过目标电压，则获得检测电压和目标电压之间的差B与检测电压与估计值之间的差C，并且通过将反馈增益乘以比率B来改变反馈增益 / C之间的这些差异。