公开(公告)号：US20090237306A1

公开(公告)日：2009-09-24

申请号：US12095853

申请日：2006-11-30

申请人： Jau-Jr Lin ,  Hsin-Ta Wu ,  Kenneth K. O

发明人： Jau-Jr Lin ,  Hsin-Ta Wu ,  Kenneth K. O

IPC分类号： H01Q1/38 ,  H01Q23/00

CPC分类号： H01Q23/00 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q9/30

摘要： A compact integrated monopole antenna is provided, where the antenna can include a bulk semiconducting substrate, an electrically conductive antenna element disposed on said substrate, where the antenna element extending continuously along an antenna element path spanning an antenna length in a first direction. The antenna also can include a plurality of spaced apart electrically conductive grounding elements disposed on the substrate, where a first of the plurality of grounding elements is disposed on a first side of the antenna path along the antenna length and a second of the plurality of grounding elements is disposed on the other side of the antenna path along the antenna length, where the plurality of grounding elements is configured to effectively lengthen the antenna length as compared to a linear ground plane.

摘要翻译： 提供了一种紧凑的集成单极天线，其中天线可以包括体半导体衬底，设置在所述衬底上的导电天线元件，其中天线元件沿着沿第一方向的天线长度的天线元件路径连续延伸。 天线还可以包括设置在基板上的多个间隔开的导电接地元件，其中多个接地元件中的第一个接地元件沿着天线长度设置在天线路径的第一侧上，并且多个接地中的第二接地元件 元件沿着天线长度设置在天线路径的另一侧上，其中多个接地元件被配置为与线性接地平面相比有效地延长天线长度。

公开(公告)号：US07466998B2

公开(公告)日：2008-12-16

申请号：US10836524

申请日：2004-04-30

申请人： Kenneth K. O ,  Jesal Mehta

发明人： Kenneth K. O ,  Jesal Mehta

IPC分类号： H04M1/00

CPC分类号： H04B15/02 ,  H01Q1/38

摘要： An integrated circuit layout and architecture for reduced noise coupling between circuitry and on-chip antenna for wireless communications includes a monolithic semiconducting substrate having a plurality of integrated devices including a transmitter and/or a receiver. At least one on-chip balanced antenna is formed in or on the substrate. A balanced antenna feed structure electrically connects the antenna to the transmitter or receiver. At least one integrated device is substantially symmetrically disposed on the substrate relative to the on-chip antenna(s). The device(s) selected for substantially symmetrically placement are preferably those which generate the largest noise coupling.

摘要翻译： 用于无线通信的电路和片上天线之间的用于减少噪声耦合的集成电路布局和架构包括具有包括发射器和/或接收器的多个集成器件的单片半导体衬底。 在衬底中或衬底上形成至少一个片上平衡天线。 平衡天线馈电结构将天线电连接到发射器或接收器。 至少一个集成器件相对于片上天线基本对称地布置在衬底上。 选择用于基本上对称放置的装置优选地是产生最大噪声耦合的装置。

公开(公告)号：US08885773B2

公开(公告)日：2014-11-11

申请号：US13092880

申请日：2011-04-22

申请人： Choong Yul Cha ,  Kenneth K. O

发明人： Choong Yul Cha ,  Kenneth K. O

IPC分类号： H03D1/24 ,  H04L27/227 ,  H04L27/00

CPC分类号： H04L27/2272 ,  H04L2027/0028 ,  H04L2027/0055

摘要： An ultra low power radio receiver architecture based on phase locked loop is provided. Embodiments of an ultra low power radio receiver architecture based on phase locked loop can detect a complex modulated MSK signal with only a single path receiver chain. According to an embodiment of the present invention, the overall power consumption of the radio receiver in the present invention can be reduced by almost fifty percent compared to that of the conventional complex path radio receiver architecture. The radio receiver architecture of the invention is suitable for the ultra low power radio application such as wireless sensor networks (WSN).

摘要翻译： 提供了一种基于锁相环的超低功耗无线电接收机架构。 基于锁相环的超低功率无线电接收器架构的实施例可以仅使用单个路径接收器链来检测复数调制的MSK信号。 根据本发明的实施例，与传统的复杂路径无线电接收机架构相比，本发明中的无线电接收机的总功耗可以减少近百分之五十。 本发明的无线电接收机架构适用于诸如无线传感器网络（WSN）的超低功率无线电应用。

公开(公告)号：US5866462A

公开(公告)日：1999-02-02

申请号：US536338

申请日：1995-09-29

申请人： Curtis Tsai ,  Kenneth K. O ,  Brad W. Scharf

发明人： Curtis Tsai ,  Kenneth K. O ,  Brad W. Scharf

IPC分类号： H01L21/331

CPC分类号： H01L29/66272

摘要： Emitter widths of 0.3 .mu.m on double polysilicon bipolar transistors are achieved using O.8 .mu.m photolithography and a double spacer process. The emitter width reduction is confirmed with structural and electrical measurements. The double-spacer device exhibits superior low current f.sub.T and f.sub.max.

摘要翻译： 双晶硅双极晶体管的发射极宽度为0.3μm，采用0.8μm光刻和双重间隔工艺。 通过结构和电气测量确认发射极宽度的减小。 双隔离器具有优异的低电流fT和fmax。

公开(公告)号：US5432114A

公开(公告)日：1995-07-11

申请号：US327656

申请日：1994-10-24

申请人： Kenneth K. O

发明人： Kenneth K. O

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0922 ,  H01L21/823857

摘要： A process for fabricating an IGFET integrated circuit having two gate dielectric layers with different parameters is provided. Typically, the process is used for fabrication of dual voltage CMOS integrated circuits. The integrated circuit may include high voltage transistors having a first gate dielectric thickness and low voltage transistors having a second gate dielectric thickness. A first gate dielectric layer and a first gate layer for the high voltage transistors are formed over active regions of a substrate. The device is patterned to expose low voltage transistor areas, and the first gate dielectric layer and the first gate layer are removed in the low voltage transistor areas. Then, a second gate dielectric layer and a second gate layer for the low voltage transistors are formed on the device. The device is patterned to expose the high voltage transistor areas, and the second gate dielectric layer and the second gate layer are removed in the high voltage transistor areas. The gate dielectric layers are protected against contamination during processing and do not come in contact with photoresist.

摘要翻译： 提供了一种制造具有不同参数的两个栅极电介质层的IGFET集成电路的工艺。 通常，该工艺用于制造双电压CMOS集成电路。 集成电路可以包括具有第一栅介质厚度的高压晶体管和具有第二栅介质厚度的低压晶体管。 在基板的有源区上形成用于高电压晶体管的第一栅极介电层和第一栅极层。 将器件图案化以暴露低电压晶体管区域，并且在低电压晶体管区域中去除第一栅极介电层和第一栅极层。 然后，在器件上形成用于低压晶体管的第二栅极介电层和第二栅极层。 将器件图案化以暴露高压晶体管区域，并且在高压晶体管区域中去除第二栅极介电层和第二栅极层。 栅极电介质层在加工过程中被防止污染，并且不与光致抗蚀剂接触。

公开(公告)号：US20120114079A1

公开(公告)日：2012-05-10

申请号：US13092880

申请日：2011-04-22

申请人： Choong Yul Cha ,  Kenneth K. O

发明人： Choong Yul Cha ,  Kenneth K. O

IPC分类号： H04L27/06

CPC分类号： H04L27/2272 ,  H04L2027/0028 ,  H04L2027/0055

摘要： An ultra low power radio receiver architecture based on phase locked loop is provided. Embodiments of an ultra low power radio receiver architecture based on phase locked loop can detect a complex modulated MSK signal with only a single path receiver chain. According to an embodiment of the present invention, the overall power consumption of the radio receiver in the present invention can be reduced by almost fifty percent compared to that of the conventional complex path radio receiver architecture. The radio receiver architecture of the invention is suitable for the ultra low power radio application such as wireless sensor networks (WSN).

摘要翻译： 提供了一种基于锁相环的超低功耗无线电接收机架构。 基于锁相环的超低功率无线电接收器架构的实施例可以仅使用单个路径接收器链来检测复数调制的MSK信号。 根据本发明的实施例，与传统的复杂路径无线电接收机架构相比，本发明中的无线电接收机的总功耗可以减少近百分之五十。 本发明的无线电接收机架构适用于诸如无线传感器网络（WSN）的超低功率无线电应用。

公开(公告)号：US07167044B2

公开(公告)日：2007-01-23

申请号：US10914408

申请日：2004-08-09

申请人： Zhenbiao Li ,  Kenneth K O

发明人： Zhenbiao Li ,  Kenneth K O

IPC分类号： H03G3/20

CPC分类号： H03F1/0261 ,  H03F1/42 ,  H03F3/191 ,  H03F3/45188 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H03G1/0088

摘要： A multi-band low noise amplifier (LNA) 105 includes an input stage having at least two inputs, a first input (103) coupled to a first input transistor for receiving signals in a first frequency band and a second input (104) coupled to a second input transistor for receiving signals in a second frequency band. The second frequency band spaced apart from the first frequency band. A bias network (218) having a band select input is coupled to the first and second input transistor, wherein a signal level applied to the band select input turns on one of the input transistors and turns off the other input transistors. The LNA (105) operates in the first frequency band when the first input transistor is on and the second frequency band when the second input transistor is on. A switched resonator (216) having a control input is provided, wherein application of a control signal to the control input tunes a resonant frequency of the LNA, and provides gain select, for operation in either the first or second frequency band.

摘要翻译： 多频带低噪声放大器（LNA）105包括具有至少两个输入的输入级，耦合到用于接收第一频带中的信号的第一输入晶体管的第一输入端（103）和耦合到 用于接收第二频带中的信号的第二输入晶体管。 与第一频带间隔开的第二频带。 具有带选择输入的偏置网络（218）耦合到第一和第二输入晶体管，其中施加到频带选择输入的信号电平导通输入晶体管中的一个并且关断其它输入晶体管。 当第一输入晶体管导通时，LNA（105）在第一频带工作，当第二输入晶体管导通时，第二频带工作。 提供了具有控制输入的开关谐振器（216），其中向控制输入端施加控制信号调节LNA的谐振频率，并提供用于在第一或第二频带中操作的增益选择。

公开(公告)号：US20120205744A1

公开(公告)日：2012-08-16

申请号：US13370395

申请日：2012-02-10

申请人： Kenneth K. O ,  Chieh-Lin Wu

发明人： Kenneth K. O ,  Chieh-Lin Wu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/265

CPC分类号： H01L21/266 ,  H01L29/66772 ,  H01L29/78615

摘要： Embodiments of the invention provide SOI body-contacted transistors that can be used for high frequency analog and digital circuits. In accordance with certain embodiments of the invention, the SOI transistor gate can have an “I” shape, similar to the shape of the gate of a floating body SOI transistor. However, a body region is provided that extends perpendicular to the width direction of the gate and is contacted at an end of the extended body region. To form such a body contact structure, a source/drain implant block mask and silicide block mask are used during the formation of the source/drain regions. The source/drain implant block mask and silicide block mask can be formed on the same region, but the silicide block mask can allow for the body contact portion at the end of the extended body region to be silicided during the siliciding of the source/drain regions.

摘要翻译： 本发明的实施例提供可用于高频模拟和数字电路的SOI体接触晶体管。 根据本发明的某些实施例，SOI晶体管栅极可以具有类似于浮体SOI晶体管的栅极的形状的“I”形状。 然而，提供了一个主体区域，其垂直于栅极的宽度方向延伸并在延伸体区域的一端接触。 为了形成这种体接触结构，在源极/漏极区域的形成期间使用源/漏注入块掩模和硅化物掩模掩模。 源极/漏极注入块掩模和硅化物掩模掩模可以形成在相同的区域上，但是硅化物掩模掩模可以允许在扩散体区域的末端处的体接触部分在源极/漏极的硅化期间被硅化 地区。

公开(公告)号：US06683362B1

公开(公告)日：2004-01-27

申请号：US09645366

申请日：2000-08-24

申请人： Kenneth K. O ,  Feng-Jung Huang

发明人： Kenneth K. O ,  Feng-Jung Huang

IPC分类号： H01L2976

CPC分类号： H01L29/7839 ,  H01L27/0629 ,  H01L27/0921

摘要： The subject invention relates to a metal-semiconductor diode clamped semiconductor device and method for producing such device. A specific embodiment of the subject invention utilizes one or more Schottky barriers at, for example, the drain and/or source of at least one transistor of a field effect transistor integrated circuit. The use of one or more Schottky barriers is useful for reducing the susceptibility of latch-up for circuits having two opposite type transistors, i.e., two opposite polarity carriers, in which the two transistors are in close enough proximity to experience latch-up. This can allow the spacing between n- and p-type transistors to be reduced, thus reducing the area of the circuit. The subject invention can also allow the elimination of a metal contact by utilizing the metal layer used to form the metal-semiconductor junction in a complementary IGFET structure, to further reduce the circuit area. The subject invention is applicable to complementary metal oxide silicon (CMOS) devices. Advantageously, the manufacturing process required to produce the subject devices can require minimal adjustments to the standard processing steps used in conventional CMOS processing.

摘要翻译： 本发明涉及一种金属半导体二极管钳位半导体器件及其制造方法。 本发明的具体实施例在例如场效应晶体管集成电路的至少一个晶体管的漏极和/或源极处使用一个或多个肖特基势垒。 使用一个或多个肖特基势垒对于减小具有两个相反型晶体管的电路（即两个相反极性的载流子）的闩锁的敏感性是有用的，其中两个晶体管足够接近以经历闩锁。 这可以使n型和p型晶体管之间的间距减小，从而减小电路的面积。 本发明还可以通过利用用于在互补IGFET结构中形成金属 - 半导体结的金属层来消除金属接触，以进一步减小电路面积。 本发明可应用于互补金属氧化物硅（CMOS）器件。 有利的是，生产目标装置所需的制造过程可能需要对常规CMOS处理中使用的标准处理步骤的最小调整。

公开(公告)号：US4829359A

公开(公告)日：1989-05-09

申请号：US55558

申请日：1987-05-29

申请人： Kenneth K. O ,  Lawrence G. Pearce ,  Dyer A. Matlock

发明人： Kenneth K. O ,  Lawrence G. Pearce ,  Dyer A. Matlock

IPC分类号： H01L27/092

CPC分类号： H01L27/0927

摘要： The separation constraint between the respective junctions formed between the drain regions of the complementary transistors and the semiconductor material in which they are formed is obviated by a structure which permits the respective drain regions of the opposite conductivity type transistors to have a reduced (effecting to zero) mutual separation and, at the same time, prevent the depletion regions fomed between the junctions defined by these source regions and the semiconductor material in which they are formed from spreading into contact with one another and thereby shorting the transistors together. This objective is achieved by a structure in which the source regions of the respective P and N channel transistors are formed so as to directly abut against one another and to be contiguous with a layer of buried dielectric isolation therebeneath. The buried dielectric layer extends from the bottom portions of the drain regions to a prescribed depth in each of the P-well region and the N-type substrate, so as to effectively provide a barrier between depletion region associated with the junction defined by the P well and N substrate the depletion regions formed between the N+ drain region and the P-well and the P+ drain region and the N-type substrate.

摘要翻译： 在互补晶体管的漏极区域和形成它们的半导体材料之间形成的各个结之间的分离约束被允许相反导电型晶体管的相应漏极区域减小（影响为零）的结构所消除 ）相互分离，并且同时防止由这些源极区域限定的结与其形成的半导体材料之间的耗尽区域彼此扩散接触，从而将晶体管短路。 该目的是通过这样的结构实现的：其中，各个P沟道晶体管和N沟道晶体管的源极区域形成为彼此直接邻接并且与其旁边的埋入介质隔离层邻接。 掩埋电介质层从漏极区域的底部延伸到每个P阱区域和N型衬底中规定的深度，从而有效地提供与由P形成的连接点相关联的耗尽区域之间的势垒 阱和N衬底在N +漏极区和P阱以及P +漏极区和N型衬底之间形成的耗尽区。