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1.发明申请ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS 失效高速总线上的错误纠正代码保护的静态位通信公开(公告)号：US20120272119A1
公开(公告)日：2012-10-25
申请号：US13535574
申请日：2012-06-28
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译： 提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。 通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。 通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。
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公开(公告)号：US08245105B2
公开(公告)日：2012-08-14
申请号：US12166235
申请日：2008-07-01
IPC分类号： H03M13/00
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0781 , G06F11/1004 , G11C5/04 , G11C29/70 , G11C2029/0409 , G11C2029/0411
摘要： A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device.
摘要翻译： 一种用于提供具有增强的可靠性的级联互连存储器系统的集线器设备，存储器系统和方法。 集线器设备包括与高速总线的接口，用于与存储器控制器进行通信。 存储器控制器和集线器设备包括在级联互连存储器系统中，并且高速总线包括位通道和一个或多个时钟通道。 集线器设备还包括与存储器控制器通信并可由服务接口读取的双向故障信号线。 集线器设备还包括用于存储关于在集线器设备处检测到的故障的信息的故障隔离寄存器（FIR），该信息包括检测到的故障的严重性级别。 此外，集线器设备包括用于响应在集线器设备处检测到的故障的错误恢复逻辑。
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3.发明申请PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY 有权在具有INDETERMINATE读取数据延迟的存储器系统中提供帧起始指示公开(公告)号：US20120151171A1
公开(公告)日：2012-06-14
申请号：US13397819
申请日：2012-02-16
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A memory system, having indeterminate read data latency, that includes a memory controller and one or more hub devices. The memory controller is configured for receiving data transfers via an upstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting a frame start indicator. The data frame includes an identification tag that is utilized by the memory controller to associate the data frame with a corresponding read instruction issued by the memory controller. The one or more hub devices are in communication with the memory controller in a cascade interconnect manner via the upstream channel and a downstream channel. Each hub device is configured for receiving the data transfers via the upstream channel or the downstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting the frame start indicator.
摘要翻译： 具有不确定的读取数据延迟的存储器系统，其包括存储器控制器和一个或多个集线器设备。 存储器控制器被配置为经由上游信道接收数据传输，并且通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。 数据帧包括由存储器控制器用于将数据帧与由存储器控制器发出的相应读取指令相关联的识别标签。 一个或多个集线器设备经由上游信道和下游信道以级联互连方式与存储器控制器通信。 每个集线器设备被配置用于经由上游信道或下游信道接收数据传输，并且用于通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。
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公开(公告)号：US20110320914A1
公开(公告)日：2011-12-29
申请号：US12822503
申请日：2010-06-24
申请人： Luiz C. Alves , Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
发明人： Luiz C. Alves , Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
IPC分类号： G06F11/10
CPC分类号： G06F11/1004 , G06F11/108
摘要： Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.
摘要翻译： 在包括存储器控制器的冗余存储器系统中的错误校正和检测; 与存储器控制器通信的多个存储器通道，存储器通道包括多个存储器件; 用于检测存储器通道之一的循环冗余码（CRC）机制已经失败，并用于将存储器通道标记为故障存储器通道; 和纠错码（ECC）机制。 ECC被配置为忽略标记的存储器通道并且用于检测和校正位于一个或多个其它存储器通道上的存储器设备上的附加存储器件故障，从而允许存储器系统在存在存储器通道的情况下继续运行不受损害 失败。
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公开(公告)号：US20110320869A1
公开(公告)日：2011-12-29
申请号：US12822964
申请日：2010-06-24
申请人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
发明人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
CPC分类号： G06F11/1666 , G06F11/1044 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels.
摘要翻译： 在包括存储器控制器，与存储器控制器通信的多个存储器通道，用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供均匀恢复。 错误恢复机制被配置为用于接收故障存储器通道的通知，用于阻止新的操作在存储器通道上启动，以完成存储器通道上的任何未决操作，用于在存储器通道上执行恢复操作并启动 至少在存储器通道的第一子集上进行新的操作。 存储器系统能够与存储器通道的第一子集一起操作。
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公开(公告)号：US20110320864A1
公开(公告)日：2011-12-29
申请号：US12822968
申请日：2010-06-24
申请人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
发明人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
CPC分类号： G06F11/2053 , G06F11/073 , G06F11/0793 , G06F11/1004 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/1666 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing in response to the removing any stale data being complete.
摘要翻译： 在包括存储器控制器，与存储器控制器通信的多个存储器通道，配置用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供异构恢复。 错误恢复机制被配置为用于接收故障存储器通道的通知，用于在其他存储器通道执行正常的系统操作时对故障存储器通道执行恢复操作，以使恢复的通道与其它存储器通道重新进入操作模式， 存储操作，用于继续标记恢复的通道以防止陈旧的数据，用于在恢复操作完成之后去除任何陈旧的数据，以及用于去除恢复的通道上的标记，以允许所有存储器通道的正常系统操作， 删除，以响应删除任何陈旧的数据完成。
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公开(公告)号：US08086783B2
公开(公告)日：2011-12-27
申请号：US12390731
申请日：2009-02-23
IPC分类号： G06F12/00
CPC分类号： G06F11/1004 , G06F12/0886
摘要： A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank includes a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments. The memory system also includes a memory controller in communication with the multiple memory channels. The memory controller distributes an access request across the memory channels to access a full rank. The full rank includes at least two of the partial ranks on separate memory channels. Partial ranks on a common memory module can be concurrently accessed. The memory modules can use at least one checksum memory device as a dedicated checksum memory device or a shared checksum memory device between at least two of the concurrently accessible partial ranks.
摘要翻译： 提供了高可用性的内存系统。 存储器系统包括多个存储器通道。 每个存储器通道包括至少一个存储器模块，其中存储器件被组织为耦合到存储器设备总线段的部分等级。 每个部分等级包括作为存储器设备总线段的子集上的子信道可访问的存储器件的子集。 存储器系统还包括与多个存储器通道通信的存储器控制器。 存储器控制器通过存储器通道分配访问请求以访问完整等级。 完整等级包括在独立内存通道上的至少两个部分等级。 可以同时访问公共内存模块上的部分排名。 存储器模块可以在至少两个可同时访问的部分等级之间使用至少一个校验和存储器设备作为专用校验和存储器设备或共享校验和存储器设备。
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公开(公告)号：US20110228622A1
公开(公告)日：2011-09-22
申请号：US12725822
申请日：2010-03-17
申请人： Paul W. COTEUS , Kevin C. GOWER , Kyu-Hyoun KIM
发明人： Paul W. COTEUS , Kevin C. GOWER , Kyu-Hyoun KIM
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A memory chip comprises an internal voltage regulator that is selectively enabled/disabled to regulate an external voltage used by the memory chip subunit.
摘要翻译： 存储器芯片包括内部电压调节器，其被选择性地使能/禁止以调节由存储器芯片子单元使用的外部电压。
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9.发明授权System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency 失效通过允许存储器通道以独立于存储器件频率的频率工作来增加存储器通道的总体带宽的系统公开(公告)号：US07925826B2
公开(公告)日：2011-04-12
申请号：US12019095
申请日：2008-01-24
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： A memory system is provided that increases the overall bandwidth of a memory channel by operating the memory channel at a independent frequency. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. Using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth, which is independent of the second operating frequency.
摘要翻译： 提供了一种存储器系统，其通过以独立频率操作存储器通道来增加存储器通道的总体带宽。 存储器系统包括集成在存储器模块中的存储器集线器设备。 存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从外部存储器控制器接收存储器访问命令。 存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。 存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。 通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，实现异步边界。 使用异步边界，存储通道以最大设计的工作带宽运行，独立于第二个工作频率。
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公开(公告)号：US07895374B2
公开(公告)日：2011-02-22
申请号：US12165809
申请日：2008-07-01
CPC分类号： G06F13/4243 , G06F11/2007 , G06F11/2017 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译： 用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。 通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。 该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段 。
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