公开(公告)号：US07595241B2

公开(公告)日：2009-09-29

申请号：US11466488

申请日：2006-08-23

申请人： Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Larry Burton Rowland ,  Jesse Berkley Tucker ,  Stephen Daley Arthur ,  Zachary Matthew Stum

发明人： Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Larry Burton Rowland ,  Jesse Berkley Tucker ,  Stephen Daley Arthur ,  Zachary Matthew Stum

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068

摘要： A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

摘要翻译： 形成垂直MOSFET器件的方法包括在漂移层衬底内形成沟槽，漂移层包括第一极性类型，沟槽通常限定与第一极性类型相反的第二极性类型的阱区。 欧姆接触层形成在沟槽的底表面内，欧姆接触层包括第二极性类型的材料。 在漂移层，沟槽的侧壁表面和欧姆接触层上外延生长第二极性类型的层。 第一极性类型的层在第二极性类型的外延生长层上外延生长，以便重新填充沟槽，并且将第一和第二极性类型的外延生长层平坦化，以暴露出第二极性类型的上表面 漂移层基板。

公开(公告)号：US20080146004A1

公开(公告)日：2008-06-19

申请号：US11610199

申请日：2006-12-13

申请人： Kevin Sean Matocha ,  Vinayak Tilak ,  Stephen Daley Arthur ,  Zachary Matthew Stum

发明人： Kevin Sean Matocha ,  Vinayak Tilak ,  Stephen Daley Arthur ,  Zachary Matthew Stum

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/0465 ,  H01L29/66068

摘要： A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.

摘要翻译： 公开了一种制造SiC MOSFET的方法。 该方法包括在衬底上生长SiC外延层，平面化SiC外延层以提供平坦化的SiC外延层，以及形成与平坦化的外延层接触的栅极电介质层。

公开(公告)号：US20080108190A1

公开(公告)日：2008-05-08

申请号：US11593317

申请日：2006-11-06

申请人： Kevin Sean Matocha

发明人： Kevin Sean Matocha

IPC分类号： H01L21/8234

CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/7827

摘要： The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800 degrees Celsius. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 micrometers. A vertical SiC MOSFET is also provided.

摘要翻译： 本发明提供一种制造金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：在碳化硅层上形成源极区域并退火源极区域。 在源区和碳化硅层上形成栅氧化层。 该方法还包括在栅极氧化物层上设置栅电极，并在栅电极和栅极氧化物层上设置电介质层。 该方法还包括蚀刻介电层的一部分和栅极氧化物层的一部分以在栅电极上形成侧壁。 金属层设置在栅电极，侧壁和源极区上。 该方法还包括通过使金属层经受至少约800摄氏度的温度来形成栅极接触和源极接触。 栅极接触和源极接触包括金属硅化物。 栅极接触点和源极接触点之间的距离小于约0.6微米。 还提供了一个垂直的SiC MOSFET。

公开(公告)号：US08217398B2

公开(公告)日：2012-07-10

申请号：US12251866

申请日：2008-10-15

申请人： Victor Lienkong Lou ,  Kevin Sean Matocha ,  Gregory Thomas Dunne

发明人： Victor Lienkong Lou ,  Kevin Sean Matocha ,  Gregory Thomas Dunne

IPC分类号： H01L29/15 ,  H01L21/31

CPC分类号： H01L29/7802 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/049 ,  H01L21/31658 ,  H01L29/66068 ,  H01L29/78

摘要： Methods are provided for improving inversion layer mobility and providing low defect density in a semiconductor device based upon a silicon carbide (SiC) substrate. More specifically, embodiments of the present method provide for the formation of a gate oxide on a silicon carbide substrate comprising oxidizing the substrate with a gaseous mixture comprising oxygen at a temperature of at least about 1300° C. Semiconductor devices, such as MOSFETS, based upon a substrate treated according to the present method are expected to have inversion layer mobilities of at least about 12 cm2/Vs.

摘要翻译： 提供了用于在基于碳化硅（SiC）衬底的半导体器件中改善反型层迁移率和提供低缺陷密度的方法。 更具体地，本方法的实施例提供了在碳化硅衬底上形成栅极氧化物，包括在至少约1300℃的温度下，用包含氧的气​​体混合物氧化衬底。基于MOSFET的半导体器件 在根据本方法处理的基底上，期望具有至少约12cm 2 / Vs的反转层迁移率。

公开(公告)号：US20120171824A1

公开(公告)日：2012-07-05

申请号：US13418566

申请日：2012-03-13

申请人： Vinayak Tilak ,  Alexei Vertiatchikh ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Siddharth Rajan

发明人： Vinayak Tilak ,  Alexei Vertiatchikh ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Siddharth Rajan

IPC分类号： H01L21/335

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/207

摘要： A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.

摘要翻译： 提供了一种制造异质结构器件的方法，其包括将离子注入到多层结构的表面的一部分中。 碘离子注入第一区域和第二区域之间以形成第三区域。 电荷从第三区域中的二维电子气（2DEG）通道中消耗，以形成从第一区域到第二区域的可逆的非导电通路。 在向靠近第三区域的栅电极施加电压电位时，允许电流从第一区域流到第二区域。

公开(公告)号：US20090242901A1

公开(公告)日：2009-10-01

申请号：US12483469

申请日：2009-06-12

申请人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

发明人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

IPC分类号： H01L29/24 ,  H01L21/285 ,  H01L29/772

CPC分类号： H01L29/4975 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/872

摘要： The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.

摘要翻译： 本发明提供一种制造金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：在碳化硅层上形成源极区域并退火源极区域。 在源区和碳化硅层上形成栅氧化层。 该方法还包括在栅极氧化物层上设置栅电极，并在栅电极和栅极氧化物层上设置电介质层。 该方法还包括蚀刻介电层的一部分和栅极氧化物层的一部分以在栅电极上形成侧壁。 金属层设置在栅电极，侧壁和源极区上。 该方法还包括通过使金属层经受至少约800℃的温度来形成栅极接触和源极接触。栅极接触和源极接触包括金属硅化物。 栅极触点与源极之间的距离小于0.6μm。 还提供了一个垂直的SiC MOSFET。

公开(公告)号：US20090140293A1

公开(公告)日：2009-06-04

申请号：US11946959

申请日：2007-11-29

申请人： Alexei Vertiatchikh ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Vinayak Tilak ,  Siddharth Rajan ,  Ho-Young Cha

发明人： Alexei Vertiatchikh ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Vinayak Tilak ,  Siddharth Rajan ,  Ho-Young Cha

IPC分类号： H01L29/778

CPC分类号： H01L29/7786 ,  H01L29/2003

摘要： A heterostructure device or article includes a carrier transport layer, a back channel layer and a barrier layer. The carrier transport layer has a first surface and a second surface opposing to the first surface. The back channel layer is secured to the first surface of the carrier transport layer and the barrier layer is secured to the second surface of the carrier transport layer. Each of the carrier transport layer, the back channel layer and the barrier layer comprises an aluminum gallium nitride alloy. The article further includes a 2D electron gas at an interface of the second surface of the carrier transport layer and a surface of the barrier layer. The 2D electron gas is defined by a bandgap differential at an interface, which allows for electron mobility. A system includes a heterostructure field effect transistor that includes the article.

摘要翻译： 异质结构器件或制品包括载流子传输层，背沟道层和阻挡层。 载流子传输层具有与第一表面相对的第一表面和第二表面。 背沟道层被固定到载流子传输层的第一表面，并且阻挡层固定到载流子传输层的第二表面。 载流子传输层，背沟道层和阻挡层中的每一个包括氮化镓铝合金。 该制品还包括在载流子传输层的第二表面和势垒层的表面的界面处的2D电子气体。 2D电子气体由界面处的带隙差分限定，这允许电子迁移率。 一种系统包括包括该物品的异质结构场效应晶体管。

公开(公告)号：US07521732B2

公开(公告)日：2009-04-21

申请号：US11283451

申请日：2005-11-18

申请人： Kevin Sean Matocha ,  Vinayak Tilak

发明人： Kevin Sean Matocha ,  Vinayak Tilak

IPC分类号： H01L29/20

CPC分类号： H01L29/7787 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/7788 ,  H01L29/7789

摘要： A vertical heterostructure field effect transistor including a first layer having a first material, and the first material having a hexagonal crystal lattice structure defining a first bandgap and one or more non-polar planes is provided. The transistor further includes a second layer that is adjacent to the first layer having a second material. Further, the second layer has a first surface and a second surface, and a portion of the second layer first surface is coupled to the surface of the first layer to form a two dimensional charge gas and to define a first region. The second material may have a second bandgap that is different than the first bandgap. Furthermore, the transistor may include a conductive layer that is disposed in the trench and is interposed between the first region and a second region that is not in electrical communication with the first region if no electrical potential is applied to the conductive layer, and an electrical potential applied to the conductive layer allows electrical communication from the first region to the second region.

摘要翻译： 提供了一种垂直异质结场效应晶体管，其包括具有第一材料的第一层，并且提供了具有限定第一带隙和一个或多个非极性平面的六方晶格结构的第一材料。 所述晶体管还包括与所述第一层相邻的第二层，所述第二层具有第二材料。 此外，第二层具有第一表面和第二表面，并且第二层第一表面的一部分耦合到第一层的表面以形成二维充电气体并限定第一区域。 第二材料可以具有与第一带隙不同的第二带隙。 此外，晶体管可以包括设置在沟槽中并且如果没有电位施加到导电层的第一区域和不与第一区域电连通的第二区域的导电层， 施加到导电层的电位允许从第一区域到第二区域的电连通。

公开(公告)号：US20080142811A1

公开(公告)日：2008-06-19

申请号：US11637991

申请日：2006-12-13

申请人： Kevin Sean Matocha ,  Larry Burton Rowland

发明人： Kevin Sean Matocha ,  Larry Burton Rowland

IPC分类号： H01L29/24 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66712

摘要： A vertical MOSFET is disclosed. The MOSFET includes a gate dielectric region, a drift region having a drift region dopant concentration profile of a first conductivity type, and a JFET region having a JFET region dopant concentration profile of the first conductivity type adjacent to the gate dielectric region and disposed over the drift region. The JFET region dopant concentration profile is different from the drift region dopant concentration profile. A method for fabricating a vertical MOSFET is also disclosed.

摘要翻译： 公开了一种垂直MOSFET。 MOSFET包括栅极电介质区域，具有第一导电类型的漂移区掺杂浓度分布的漂移区域和具有与栅介电区域相邻的第一导电类型的JFET区掺杂浓度分布的JFET区域， 漂移区。 JFET区掺杂剂浓度分布与漂移区掺杂浓度分布不同。 还公开了一种用于制造垂直MOSFET的方法。

公开(公告)号：US20080050876A1

公开(公告)日：2008-02-28

申请号：US11466488

申请日：2006-08-23

申请人： Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Larry Burton Rowland ,  Jesse Berkley Tucker ,  Stephen Daley Arthur ,  Zachary Matthew Stum

发明人： Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Larry Burton Rowland ,  Jesse Berkley Tucker ,  Stephen Daley Arthur ,  Zachary Matthew Stum

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068

摘要： A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

摘要翻译： 形成垂直MOSFET器件的方法包括在漂移层衬底内形成沟槽，漂移层包括第一极性类型，沟槽通常限定与第一极性类型相反的第二极性类型的阱区。 欧姆接触层形成在沟槽的底表面内，欧姆接触层包括第二极性类型的材料。 在漂移层，沟槽的侧壁表面和欧姆接触层上外延生长第二极性类型的层。 第一极性类型的层在第二极性类型的外延生长层上外延生长，以便重新填充沟槽，并且将第一和第二极性类型的外延生长层平坦化，以暴露出第二极性类型的上表面 漂移层基板。