公开(公告)号：US07633288B2

公开(公告)日：2009-12-15

申请号：US11527378

申请日：2006-09-27

申请人： Ae-Yong Chung ,  Eun-Seok Lee ,  Ki-Sang Kang ,  Kyeong-Seon Shin

发明人： Ae-Yong Chung ,  Eun-Seok Lee ,  Ki-Sang Kang ,  Kyeong-Seon Shin

IPC分类号： G01R31/28 ,  G01R31/26

CPC分类号： G01R31/2893

摘要： Example embodiments may provide a method of testing semiconductor devices by identifying units of lots and a test tray such that a plurality of lots having semiconductor devices may be continuously tested by a handler. Example embodiments may also provide a handler used to test the semiconductor devices.

摘要翻译： 示例性实施例可以提供通过识别批量单元和测试托盘来测试半导体器件的方法，使得具有半导体器件的多个批次可以由处理器连续测试。 示例性实施例还可以提供用于测试半导体器件的处理器。

公开(公告)号：US20070236235A1

公开(公告)日：2007-10-11

申请号：US11727938

申请日：2007-03-29

申请人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

发明人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

IPC分类号： G01R31/02

CPC分类号： G01R31/2865 ,  G01R31/2862

摘要： A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.

摘要翻译： 用于在测试环境中保持稳定温度的半导体器件测试处理器可以包括加载单元，其加载安装在测试托盘上的多个半导体器件; 浸泡室，其构造成从加载单元接收测试托盘并在老化温度下老化半导体器件; 以及被配置为接收和测试老化的半导体器件的测试室。 测试室可以包括：测试板; 第一个房间 第二个房间 连接到第一和第二室的一个或多个管道，允许温度控制介质在第一和第二室之间流动; 脱泡室，其进一步老化测试的半导体器件，使得测试的半导体器件基本上回到环境温度; 以及分类和卸载单元，其根据测试结果对测试的半导体器件进行排序，并且对排序的半导体器件进行卸载。

公开(公告)号：US20070075719A1

公开(公告)日：2007-04-05

申请号：US11527378

申请日：2006-09-27

申请人： Ae-Yong Chung ,  Eun-Seok Lee ,  Ki-Sang Kang ,  Kyeong-Seon Shin

发明人： Ae-Yong Chung ,  Eun-Seok Lee ,  Ki-Sang Kang ,  Kyeong-Seon Shin

IPC分类号： G01R31/26

CPC分类号： G01R31/2893

摘要： Example embodiments may provide a method of testing semiconductor devices by identifying units of lots and a test tray such that a plurality of lots having semiconductor devices may be continuously tested by a handler. Example embodiments may also provide a handler used to test the semiconductor devices.

摘要翻译： 示例性实施例可以提供通过识别批量单元和测试托盘来测试半导体器件的方法，使得具有半导体器件的多个批次可以由处理器连续测试。 示例性实施例还可以提供用于测试半导体器件的处理器。

公开(公告)号：US07103493B2

公开(公告)日：2006-09-05

申请号：US10851151

申请日：2004-05-24

申请人： Ki-Sang Kang ,  Tsutomu Akiyama ,  Je-Young Park

发明人： Ki-Sang Kang ,  Tsutomu Akiyama ,  Je-Young Park

IPC分类号： G01R31/00

CPC分类号： G11C29/56004 ,  G11C29/56 ,  G11C2029/1208

摘要： Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector, a failure memory, a failure bit counter and a controller for coordinating the operation of the various elements. Depending on the signals received from the controller, the pattern generator will generate background pattern(s) or test patterns and address information that are, in turn, output to the memory device under test and the selector. During functional testing of the memory device, failure data is accumulated in a failure memory and subsequently output to a failure bit counter using address information from the address pointer while the background or test pattern is being written to the memory device.

摘要翻译： 提供了一种操作这样的装置的存储器件测试装置和方法，其可以减少测试诸如DRAM的存储器件所需的时间。 存储器测试装置包括模式发生器，测试头，地址指针，选择器，故障存储器，故障位计数器和用于协调各种元件的操作的控制器。 根据从控制器接收到的信号，模式发生器将产生背景模式或测试模式和地址信息，这些模式和地址信息又被输出到被测存储器件和选择器。 在存储器件的功能测试期间，故障数据被累积在故障存储器中，随后当将背景或测试模式写入存储器件时，使用来自地址指针的地址信息将其输出到故障位计数器。

公开(公告)号：US06625766B1

公开(公告)日：2003-09-23

申请号：US09512158

申请日：2000-02-24

申请人： Se-Jang Oh ,  Ki-Sang Kang

发明人： Se-Jang Oh ,  Ki-Sang Kang

IPC分类号： G11C2900

CPC分类号： G11C29/20 ,  G11C2029/0405

摘要： A test method of a tester of a semiconductor memory device which includes recording a test pattern into the semiconductor memory device, reading the recorded test pattern to compare with a expected pattern, detecting information on a defect of the semiconductor memory device with a result of the comparison and interpreting the information on the defect of the semiconductor memory device, the method comprising the steps of: setting up minimum and maximum values relevant to a desired capacity of the semiconductor memory device to be tested; counting up from the preset minimum to the preset maximum values; generating a carry signal by comparing the preset maximum value with the counted value when the counted value gets to the preset maximum value; and resetting a value to be counted if the carry signal is generated, to thereby generate addresses of the semiconductor memory device, and a tester of the semiconductor memory device comprising: minimum and maximum address registering means for saving minimum and maximum address values relevant to a desired capacity of the semiconductor memory device to be tested; address counting means for increasingly counting from the minimum value to generate addresses; and carry signal generating means for generating carry signals, if the addresses output from the address counting means and a signal output from the maximum address registering means are the same, to thereby reset the address counting means, so that a user of the tester does not have to make a new test program, providing convenience in performing a test and improving reliability in results of the test.

摘要翻译： 一种半导体存储器件的测试器的测试方法，包括将测试图案记录到半导体存储器件中，读取记录的测试图案以与预期图案进行比较，检测关于半导体存储器件的缺陷的信息，结果是 比较和解释关于半导体存储器件的缺陷的信息，该方法包括以下步骤：设置与要测试的半导体存储器件的期望容量相关的最小值和最大值; 从预设最小值到预设最大值; 当计数值达到预设最大值时，通过将预设最大值与计数值进行比较来产生进位信号; 并且如果产生进位信号，则重置要计数的值，从而生成半导体存储器件的地址，以及半导体存储器件的测试器，包括：最小和最大地址寄存装置，用于保存与a相关的最小和最大地址值 要测试的半导体存储器件的期望容量; 地址计数装置，用于从最小值逐渐计数以产生地址; 以及用于产生进位信号的进位信号产生装置，如果从地址计数装置输出的地址和从最大地址登记装置输出的信号相同，从而复位地址计数装置，使得测试仪的用户不 必须制定一个新的测试程序，提供方便的测试和提高测试结果的可靠性。

公开(公告)号：US06507801B1

公开(公告)日：2003-01-14

申请号：US09697026

申请日：2000-10-25

申请人： Se-Jang Oh ,  Ki-Sang Kang ,  Jeong-Ho Bang

发明人： Se-Jang Oh ,  Ki-Sang Kang ,  Jeong-Ho Bang

IPC分类号： G06F300

CPC分类号： G01R31/31707 ,  G01R31/3183 ,  G01R31/318371

摘要： The present invention relates to a semiconductor device testing system having an advanced testing capability for performing tests on a semiconductor device. A system frame includes both normal and high-speed testing formatters, and a test head is arranged in electrical communication with the system frame. Normal PIN drivers are included to operate the testing system at a first frequency to transmit the signals required to perform tests at a normal speed. High-speed PIN drivers are also included to operate the testing system at a second frequency, higher than the first frequency, to transmit the signals required to perform tests at a higher speed. In this manner, the testing system of this invention is able-to achieve superior testing performance while reducing the overall system production cost.

摘要翻译： 本发明涉及具有用于对半导体器件进行测试的先进测试能力的半导体器件测试系统。 系统框架包括正常和高速测试格式化程序，测试头与系统框架电气通信。 包括正常PIN驱动程序，以第一频率操作测试系统，以正常速度传输执行测试所需的信号。 还包括高速PIN驱动程序，以高于第一个频率的第二个频率操作测试系统，以更高速度传输执行测试所需的信号。 以这种方式，本发明的测试系统能够在降低整个系统生产成本的同时实现优异的测试性能。

公开(公告)号：US06445172B1

公开(公告)日：2002-09-03

申请号：US09620016

申请日：2000-07-20

申请人： Seok-ho Park ,  Ki-sang Kang ,  Se-jang Oh

发明人： Seok-ho Park ,  Ki-sang Kang ,  Se-jang Oh

IPC分类号： G01R3128

CPC分类号： G01R31/2887

摘要： A wafer probing system, and a wafer-probing needle calibrating method using the same are provided. The system comprises a main support, a wafer chuck mounted on the main support, a needle chuck for contacting one of the plurality of needles. The needle chuck is comprised of a conductive signal line, and a shield line for shielding the signal line. Further, the system includes positioning means, for determining the position of the plurality of needles, moving means, for vertically moving the needle chuck, being coupled to the support, and means for horizontally moving the support based on the determined position of the plurality of needles. With the present invention system and method, signals applied to wafer probing needles can be accurately calibrated.

摘要翻译： 提供晶片探测系统，以及使用其的晶片探针校准方法。 该系统包括主支撑件，安装在主支架上的晶片卡盘，用于接触多个针中的一个针的针卡盘。 针卡盘由导电信号线和用于屏蔽信号线的屏蔽线组成。 此外，该系统包括用于确定多个针的位置的定位装置，用于垂直移动针卡盘的移动装置，其连接到支撑件，以及用于基于所确定的多个 针。 利用本发明的系统和方法，可以精确校准施加到晶片探针的信号。

公开(公告)号：US07886206B2

公开(公告)日：2011-02-08

申请号：US12385116

申请日：2009-03-31

申请人： Je-Young Park ,  Ki-Sang Kang

发明人： Je-Young Park ,  Ki-Sang Kang

IPC分类号： G11C29/00

CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C2029/1806 ,  G11C2029/5606

摘要： A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.

摘要翻译： 提供半导体存储器测试装置及其方法。 示例半导体存储器测试设备可以包括被配置为存储被测存储器的至少一个测试结果的故障存储器，模式选择单元，被配置为输出用于选择故障存储器的存储器地址协议的选择信号， 多个测试模式在待测存储器中是有效的，并且地址排列单元被配置为响应于从模式选择单元接收的选择信号而布置地址信号以符合所选择的存储器地址协议。

公开(公告)号：US07533310B2

公开(公告)日：2009-05-12

申请号：US11640893

申请日：2006-12-19

申请人： Je-Young Park ,  Ki-Sang Kang

发明人： Je-Young Park ,  Ki-Sang Kang

IPC分类号： G11C29/00

CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C2029/1806 ,  G11C2029/5606

摘要： A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.

摘要翻译： 提供半导体存储器测试装置及其方法。 示例半导体存储器测试设备可以包括被配置为存储被测存储器的至少一个测试结果的故障存储器，模式选择单元，被配置为输出用于选择故障存储器的存储器地址协议的选择信号， 多个测试模式在待测存储器中是有效的，并且地址排列单元被配置为响应于从模式选择单元接收的选择信号而布置地址信号以符合所选择的存储器地址协议。

公开(公告)号：US20080110809A1

公开(公告)日：2008-05-15

申请号：US11983635

申请日：2007-11-09

申请人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

发明人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

IPC分类号： G01R31/28 ,  B07C5/344 ,  G01R31/319 ,  B65G65/02

CPC分类号： H01L21/67282 ,  G01R31/2867 ,  G01R31/2893 ,  H01L21/67271 ,  Y10S414/135

摘要： A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.

摘要翻译： 提供了一种用于半导体器件的电测试的多功能处理器系统。 多功能处理器系统包括：（1）半导体器件处理部分，包括包括缓冲器的加载单元，包括单独的标记机的分拣单元和卸载单元; （2）与半导体器件处理部分分离的半导体器件测试部分包括测试室，测试室被分离成两个或更多个测试空间，并且测试室的测试空间包括位于下部的第二室 位置，位于第二室上方的第一室以及用于将第一和第二室彼此连接的管道; 和（3）独立地连接到半导体器件处理部分和半导体器件测试部分并且控制托盘信息，测试结果，标记信息和测试程序信息的主计算机。