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    MRAM with sidewall protection and method of fabrication
    2.
    发明授权
    MRAM with sidewall protection and method of fabrication 有权
    MRAM具有侧壁保护和制造方法

    公开(公告)号：US08796795B2

    公开(公告)日：2014-08-05

    申请号：US13136454

    申请日：2011-08-01

    Applicant: Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

    Inventor： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

    IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00

    CPC classification number: H01L27/222 ,  H01L27/2436 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

    Abstract: BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

    Abstract translation: 描述了BEOL存储器单元，其包括在经由蚀刻互连之前沉积的存储器件（包括例如MTJ元件）上的一个或多个侧壁保护层，以防止在层之间形成电短路。 一个实施例使用在存储器件已被图案化之后沉积的单层侧壁保护套管。 层材料被垂直地蚀刻以暴露顶部电极的上表面，同时留下围绕存储器件的其余部分的保护材料的残留层。 选择保护层的材料以抵抗用于在随后的互连过程中从通孔去除第一介电材料的蚀刻剂。 第二实施例使用双层侧壁保护，其中第一层覆盖存储元件优选是无氧电介质，并且第二层在通孔蚀刻期间保护第一层。

    MRAM Fabrication Method with Sidewall Cleaning
    3.
    发明申请
    MRAM Fabrication Method with Sidewall Cleaning 有权
    MRAM制造方法与侧壁清洁

    公开(公告)号：US20130267042A1

    公开(公告)日：2013-10-10

    申请号：US13443818

    申请日：2012-04-10

    Applicant: Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

    Inventor： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

    IPC: H01L21/02

    CPC classification number: H01L27/222 ,  H01L43/12

    Abstract: Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

    Abstract translation: 描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

    Mram etching processes
    4.
    发明申请
    Mram etching processes 有权
    摩擦蚀刻工艺

    公开(公告)号：US20130052752A1

    公开(公告)日：2013-02-28

    申请号：US13199490

    申请日：2011-08-30

    Applicant: Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger K. Malmhall

    Inventor： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger K. Malmhall

    IPC: H01L21/8246

    CPC classification number: H01L43/12 ,  H01L29/00

    Abstract: Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.

    Abstract translation: 本发明的各种实施例涉及用于制造MRAM装置中的MTJ电池的蚀刻工艺。 各种实施例可以彼此组合使用。 第一实施例在硬掩模和顶电极之间添加硬掩模缓冲层。 第二实施例使用多层蚀刻硬掩模。 第三实施例使用包括第二层如Ta之下的第一Cu层的多层顶电极结构。 第四实施例是用于底部电极去除再沉积材料同时保持更垂直侧壁蚀刻轮廓的两相蚀刻工艺。 在第一阶段中，使用碳质反应离子蚀刻去除底部电极层直到端点。 在第二阶段中，使用惰性气体和/或氧等离子体去除在先前蚀刻工艺期间沉积的聚合物。

    MRAM with sidewall protection and method of fabrication
    5.
    发明申请
    MRAM with sidewall protection and method of fabrication 有权

    公开(公告)号：US20130032907A1

    公开(公告)日：2013-02-07

    申请号：US13136454

    申请日：2011-08-01

    Applicant: Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

    Inventor： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

    IPC: H01L29/82 ,  H01L43/12

    CPC classification number: H01L27/222 ,  H01L27/2436 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

    Abstract: BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

    Twin insulator charge storage device operation and its fabrication method
    10.
    发明申请
    Twin insulator charge storage device operation and its fabrication method 有权
    双绝缘子电荷存储装置的操作及其制作方法

    公开(公告)号：US20070114597A1

    公开(公告)日：2007-05-24

    申请号：US11652888

    申请日：2007-01-12

    Applicant: Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

    Inventor： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

    IPC: H01L29/792

    CPC classification number: G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

    Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

    Abstract translation: 本发明提出了改进的双MONOS存储器件及其制造方法。 ONO层水平自对准控制门。 控制栅极和字栅之间的垂直绝缘体不包括氮化物层。 这样可以防止电子捕获的问题。 可以制造器件以通过ONO绝缘体的顶部或底部氧化物层拉出电子。 该器件还包括在控制栅极之间的升高的存储器位扩散以减小位阻。 双MONOS存储器阵列可以通过本发明的方法嵌入到标准CMOS电路中。

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