公开(公告)号：US20120074428A1

公开(公告)日：2012-03-29

申请号：US13311762

申请日：2011-12-06

Applicant: Kiyoshi Arai ,  Gourab Majumdar

Inventor： Kiyoshi Arai ,  Gourab Majumdar

IPC: H01L29/16

CPC classification number: H01L27/0664 ,  H01L21/8213 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/071 ,  H01L25/074 ,  H01L25/18 ,  H01L29/6606 ,  H01L29/861 ,  H01L29/872 ,  H01L2224/32145 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/40227 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49107 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/83801

Abstract: A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Abstract translation: 提供了一种具有安装在开关元件上的一个或多个碳化硅二极管元件的半导体模块，其中通过将开关元件中的每个二极管元件适当地布置来降低温度上升，从而为各个二极管元件提供散热路径 。 各个二极管元件布置在开关元件的非中心部分上，以便于散发由每个二极管元件产生的热量，从而降低半导体模块中的温度升高。

公开(公告)号：US07769209B2

公开(公告)日：2010-08-03

申请号：US11542570

申请日：2006-10-04

Applicant: Kazuhiro Komura ,  Kiyoshi Arai

Inventor： Kazuhiro Komura ,  Kiyoshi Arai

IPC: G06K9/00

CPC classification number: G06K9/00885 ,  G06K9/6228 ,  G06K9/6857 ,  G06K2009/00932 ,  G06Q20/3674 ,  G06Q20/40

Abstract: A biometric authentication device, which uses biometrics characteristic information to perform individual authentication, prevents declines in verification speed even when numerous biometrics information sets have been registered. A control unit registers broad characteristic quantities for blood vessel image data from an image capture device, together with characteristic data for verification. And at the time of authentication the control unit uses degrees of similarity of characteristic quantities to determine an order of verification, and performs verification of blood vessel image characteristic data in the verification order thus determined. The order of verification is determined based on captured blood vessel images, so that even when numerous characteristic data sets have been registered, verification can be performed in an order of verification based on a blood vessel image of the user, and the speed of verification can be improved.

Abstract translation: 使用生物识别特征信息进行个体认证的生物体认证装置即使在已经登记了许多生物特征信息集的情况下也能够防止验证速度的下降。 控制单元与图像捕获装置的血管图像数据一起记录广泛的特征量以及用于验证的特征数据。 并且在认证时，控制单元使用特征量的相似度来确定验证顺序，并且按照如此确定的验证顺序对血管图像特征数据进行验证。 基于捕获的血管图像确定验证顺序，使得即使已经登记了许多特征数据集，也可以基于用户的血管图像的验证顺序进行验证，并且验证速度可以 要改进

公开(公告)号：US20100075444A1

公开(公告)日：2010-03-25

申请号：US12479248

申请日：2009-06-05

Applicant: Kiyoshi Arai ,  Majumdar Gourab

Inventor： Kiyoshi Arai ,  Majumdar Gourab

IPC: H01L21/66 ,  H01L21/50

CPC classification number: G06Q50/04 ,  G06Q10/06 ,  H01L29/1608 ,  Y02P90/30

Abstract: An FOM (figure of merit) enabling evaluation from a cost aspect, as well as evaluation of electrical performance, is newly proposed to provide a method of manufacturing based on the FOM a semiconductor chip intended for a lower cost production in addition to satisfying electrical performance. An FOMC of a semiconductor chip is defined as the product of a term represented by electrical performance of a substrate S and a term represented by a semiconductor chip cost CC; the FOMC of each of the semiconductor chips on substrates SS, SC of different type is determined by calculation of the product thereof. Based on the magnitudes of the calculation results, a desired substrate is selected from the substrates SS, SC and then a semiconductor chip is fabricated by forming a semiconductor element on the desired substrate selected.

Abstract translation: 最近提出了能够从成本方面进行评估的FOM（品质因数）以及电性能的评估，以提供一种基于FOM的制造方法，该方法除了满足电性能以外，用于低成本生产的半导体芯片 。 将半导体芯片的FOMC定义为由基板S的电性能表示的项和由半导体芯片成本CC表示的项的乘积; 通过其产品的计算来确定不同类型的基板SS，SC上的每个半导体芯片的FOMC。 基于计算结果的大小，从衬底SS，SC中选择期望的衬底，然后通过在所选择的衬底上形成半导体元件来制造半导体芯片。

公开(公告)号：US5887069A

公开(公告)日：1999-03-23

申请号：US567875

申请日：1995-12-06

Applicant: Hiroshi Sakou ,  Hirohiko Sagawa ,  Masahiro Abe ,  Akira Ichikawa ,  Kiyoshi Inoue ,  Kiyoshi Arai ,  Takanori Shimura ,  Yuji Toda

Inventor： Hiroshi Sakou ,  Hirohiko Sagawa ,  Masahiro Abe ,  Akira Ichikawa ,  Kiyoshi Inoue ,  Kiyoshi Arai ,  Takanori Shimura ,  Yuji Toda

IPC: G06F17/28 ,  G06K9/00 ,  G06K9/62 ,  G06K9/68

CPC classification number: G06F17/2818 ,  G06K9/00355 ,  G06K9/6293

Abstract: In continuous sign language recognition, reference sign language patterns of good quality are generated. Continuous sign language patterns and reference sign language patterns are efficiently compressed. The compressed continuous sign language patterns are sequentially and directly matched with the compressed reference sign language patterns to recognize the sign language at high speed and with high precision. A reference sign pattern generating unit generates a reference sign language pattern by normalizing sample patterns while taking into consideration of their nonlinear compression/expansion and by calculating an average of the sample patterns. A continuous sign language recognition unit recognizes a continuous sign language at high speed by sequentially matching the continuous sign language of time sequential patterns with reference sign language patterns while allowing nonlinear expansion and compression in the time domain. A sign language translation system is provided in which a sign language as well as the facial expression or emotion of a sign language user is recognized and converted into a spoken language with emotion, and transferred in the form of texts, voices, sign languages of another type to a particular partner among a plurality of unknown system users.

Abstract translation: 在连续的手语识别中，产生了质量好的参考手语模式。 连续手语模式和参考手语模式被有效地压缩。 压缩的连续手语模式与压缩的参考手语模式顺序地和直接地匹配，以高速和高精度识别手语。 参考符号图案生成单元通过在考虑其非线性压缩/扩展并且通过计算样本图案的平均值的同时归一化样本图案来生成参考手势语言模式。 连续符号语言识别单元通过使时序模式的连续符号语言与参考手语模式顺序匹配，同时在时域中允许非线性扩展和压缩来高速识别连续符号语言。 提供了一种手语翻译系统，其中手语语言以及手语用户的面部表情或情感被识别并转换成具有情感的口语，并以文本，语音，另一种语言的手语的形式传送 类型到多个未知系统用户中的特定伙伴。

公开(公告)号：US5544050A

公开(公告)日：1996-08-06

申请号：US114083

申请日：1993-08-31

Applicant: Masahiro Abe ,  Hiroshi Sakou ,  Hirohiko Sagawa ,  Akira Ichikawa ,  Kiyoshi Inoue ,  Kiyoshi Arai ,  Takanori Shimura ,  Yuji Toda

Inventor： Masahiro Abe ,  Hiroshi Sakou ,  Hirohiko Sagawa ,  Akira Ichikawa ,  Kiyoshi Inoue ,  Kiyoshi Arai ,  Takanori Shimura ,  Yuji Toda

IPC: G09B7/02 ,  G06Q50/00 ,  G06Q50/10 ,  G06Q50/20 ,  G09B21/00 ,  G06F3/14 ,  G06F17/21 ,  G06F17/28

CPC classification number: G09B21/009

Abstract: In a sign-language learning system, the data of sign-language desired by a learner can be outputted quickly and accurately and, moreover, in the display method matching the requirements of individual learners, and the individual learners can easily make additional registration. The sign-language data are stored in a sign-language dictionary, and desired sign-language data are searched on the basis of an entry word or contents by a dictionary search device. The searched sign-language data are displayed in a display output device in accordance with a requirement of a learner by image synthesis. The sign-language data are registered by a dictionary registration device.

Abstract translation: 在手语学习系统中，可以快速，准确地输出学习者所需的手语数据，而且可以根据个人学习者的要求进行显示方式的输出，个别学习者可以轻松进行额外的注册。 符号语言数据被存储在手语字典中，并且通过字典搜索装置根据入口词或内容来搜索期望的符号语言数据。 搜索到的符号语言数据根据图像合成学习者的要求显示在显示输出装置中。 手语数据由字典登记装置登记。

公开(公告)号：US5424579A

公开(公告)日：1995-06-13

申请号：US084957

申请日：1993-07-02

Applicant: Kiyoshi Arai ,  Yoshio Takagi

Inventor： Kiyoshi Arai ,  Yoshio Takagi

IPC: H01L23/60 ,  H01L23/492 ,  H01L23/64 ,  H01L23/66 ,  H01L25/07 ,  H01L25/18 ,  H01L23/02 ,  H01L23/12 ,  H01L23/48 ,  H01L29/44

CPC classification number: H01L24/06 ,  H01L23/492 ,  H01L23/645 ,  H01L23/66 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2223/6644 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48699 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/30107

Abstract: A first composite substrate including an insulating substrate, a copper pattern, and a copper layer on opposite surfaces is mounted on a metal base plate. A second composite substrate and semiconductor chips are mounted on the first composite substrate and interconnected by wire bonding. The paths of current flowing in the wires and in a copper pattern of the second composite substrate are antiparallel to the paths of current flowing in respective corresponding portions of the first composite substrate. A semiconductor device is produced in which an increasing switching frequency does not increase a surge voltage generated in ON and OFF switching operations.

Abstract translation: 在金属基板上安装包括绝缘基板，铜图案和相对表面上的铜层的第一复合基板。 第二复合衬底和半导体芯片安装在第一复合衬底上并通过引线接合互连。 在第二复合衬底的电线和铜图案中流动的电流的路径与在第一复合衬底的相应对应部分中流动的电流的路径反平行。 制造半导体器件，其中增加的开关频率不会增加在ON和OFF开关操作中产生的浪涌电压。

公开(公告)号：US5291065A

公开(公告)日：1994-03-01

申请号：US990199

申请日：1992-12-14

Applicant: Kiyoshi Arai ,  Hirofumi Omachi

Inventor： Kiyoshi Arai ,  Hirofumi Omachi

IPC: H01L23/13 ,  H01L23/12 ,  H01L23/14 ,  H01L23/538 ,  H01L23/60 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18 ,  H01L23/16 ,  H01L39/02

CPC classification number: H01L23/552 ,  H01L23/5385 ,  H01L23/60 ,  H01L25/162 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/92247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/3025

Abstract: A patterned first metal plate (310)is joined to an upper surface of a first ceramic substrate (301), and a second metal plate (330) is joined to an emitter electrode (310E) of the first metal plate (310) through a second ceramic substrate (320). Power devices (4) are mounted on a collector electrode (310C) of the first metal plate (310), and control devices (5) are mounted on the second metal plate (330). The emitter electrode (310E) of a metal layer lies between a high-voltage circuit having the first metal plate (310) and power devices (4) and a control (low-voltage) circuit having the control devices (5) and second metal plate (330). The emitter electrode (310E) serves as a shielding material, and the electrostatic shielding effect prevents noises applied to the high-voltage circuit from being led to the control circuit, so that the faulty operations of the control devices (5) are prevented and the reliability of the semiconductor device is improved.

Abstract translation: 图案化的第一金属板（310）与第一陶瓷基板（301）的上表面接合，第二金属板（330）通过第一金属板（310）的第一金属板（310）的发射极（310E） 第二陶瓷基板（320）。 功率器件（4）安装在第一金属板（310）的集电极（310C）上，控制装置（5）安装在第二金属板（330）上。 金属层的发射电极（310E）位于具有第一金属板（310）和功率器件（4）的高压电路和具有控制装置（5）和第二金属（5）的控制（低压）电路之间 板（330）。 发射电极（310E）用作屏蔽材料，并且防止施加到高压电路的噪声被引导到控制电路的静电屏蔽效应，从而防止控制装置（5）的故障操作，并且 提高了半导体器件的可靠性。

公开(公告)号：US08213284B2

公开(公告)日：2012-07-03

申请号：US11434883

申请日：2006-05-17

Applicant: Tetsuji Kawashima ,  Yukio Shishido ,  Yoshiyuki Tokumoto ,  Toru Ifuku ,  Hiroshi Naganuma ,  Kiyoshi Arai ,  Hideho Maeda

Inventor： Tetsuji Kawashima ,  Yukio Shishido ,  Yoshiyuki Tokumoto ,  Toru Ifuku ,  Hiroshi Naganuma ,  Kiyoshi Arai ,  Hideho Maeda

IPC: G11B7/00

CPC classification number: G11B7/00736 ,  G11B7/00454 ,  G11B7/24038 ,  G11B20/1217 ,  G11B2020/1228 ,  G11B2020/1231 ,  G11B2020/1288 ,  G11B2020/1297 ,  G11B2220/216 ,  G11B2220/218 ,  G11B2220/235 ,  G11B2220/257

Abstract: A recording apparatus performs recording on an optical disc recording medium which has a plurality of recording layers and is capable of having data rewritten thereon. The recording apparatus includes recording means for performing data recording on each recording layer of the recording medium and recording controlling means for controlling the recording means so that, among the plurality of recording layers, recording of dummy data is performed preferentially starting from a recording layer intended for the final user data recording operation.

Abstract translation: 记录装置在具有多个记录层并且能够在其上重写数据的光盘记录介质上执行记录。 记录装置包括用于在记录介质的每个记录层上执行数据记录的记录装置和用于控制记录装置的记录控制装置，使得在多个记录层中，从预期的记录层开始优先执行伪数据的记录 用于最终用户数据记录操作。

公开(公告)号：US08168985B2

公开(公告)日：2012-05-01

申请号：US12543779

申请日：2009-08-19

Applicant: Kiyoshi Arai ,  Gourab Majumdar

Inventor： Kiyoshi Arai ,  Gourab Majumdar

IPC: H01L25/07 ,  H01L25/18 ,  H01L29/12

CPC classification number: H01L27/0664 ,  H01L21/8213 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/071 ,  H01L25/074 ,  H01L25/18 ,  H01L29/6606 ,  H01L29/861 ,  H01L29/872 ,  H01L2224/32145 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/40227 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49107 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/83801

Abstract: A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Abstract translation: 提供了一种具有安装在开关元件上的一个或多个碳化硅二极管元件的半导体模块，其中通过将开关元件中的每个二极管元件适当地布置来降低温度上升，从而为各个二极管元件提供散热路径 。 各个二极管元件布置在开关元件的非中心部分上，以便于散发由每个二极管元件产生的热量，从而降低半导体模块中的温度升高。

公开(公告)号：US07989227B2

公开(公告)日：2011-08-02

申请号：US12479248

申请日：2009-06-05

Applicant: Kiyoshi Arai ,  Majumdar Gourab

Inventor： Kiyoshi Arai ,  Majumdar Gourab

IPC: H01L21/00

CPC classification number: G06Q50/04 ,  G06Q10/06 ,  H01L29/1608 ,  Y02P90/30

Abstract: An FOM (figure of merit) enabling evaluation from a cost aspect, as well as evaluation of electrical performance, is newly proposed to provide a method of manufacturing based on the FOM a semiconductor chip intended for a lower cost production in addition to satisfying electrical performance. An FOMC of a semiconductor chip is defined as the product of a term represented by electrical performance of a substrate S and a term represented by a semiconductor chip cost CC; the FOMC of each of the semiconductor chips on substrates SS, SC of different type is determined by calculation of the product thereof. Based on the magnitudes of the calculation results, a desired substrate is selected from the substrates SS, SC and then a semiconductor chip is fabricated by forming a semiconductor element on the desired substrate selected.

Abstract translation: 最近提出了能够从成本方面进行评估的FOM（品质因数）以及电性能的评估，以提供一种基于FOM的制造方法，该方法除了满足电性能以外，用于低成本生产的半导体芯片 。 将半导体芯片的FOMC定义为由基板S的电性能表示的项和由半导体芯片成本CC表示的项的乘积; 通过其产品的计算来确定不同类型的基板SS，SC上的每个半导体芯片的FOMC。 基于计算结果的大小，从衬底SS，SC中选择期望的衬底，然后通过在所选择的衬底上形成半导体元件来制造半导体芯片。