公开(公告)号：US07667492B2

公开(公告)日：2010-02-23

申请号：US12004617

申请日：2007-12-21

申请人： Kiyoshi Kase ,  May Len ,  Dzung T. Tran

发明人： Kiyoshi Kase ,  May Len ,  Dzung T. Tran

IPC分类号： H03K19/094

CPC分类号： H03K19/018521

摘要： Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.

摘要翻译： 用于缓冲输入信号的方法和相应系统包括响应于输入信号低于较低阈值输出第一逻辑值。 响应于输入信号上升到较低阈值以上而输出第二逻辑值。 此后，维持第二逻辑值，直到输入超过较高阈值，然后低于较高阈值。 响应于输入信号低于较高阈值，第一逻辑值被输出并保持在第一逻辑值，直到输入低于低阈值，然后上升到低于下阈值。

公开(公告)号：US07573332B1

公开(公告)日：2009-08-11

申请号：US12039377

申请日：2008-02-28

申请人： Kiyoshi Kase

发明人： Kiyoshi Kase

IPC分类号： H03F3/45 ,  H03H11/00

CPC分类号： H03F3/45183 ,  H03F2203/45652

摘要： An amplifier comprises an amplifier stage and an active inductor. The amplifier stage has an input terminal and an output terminal. The active inductor comprises first and second resistors and first and second transistors. The first resistor has a first terminal coupled to the output terminal of the amplifier stage, and a second terminal. The second resistor has a first terminal coupled to the output terminal of the amplifier stage, and a second terminal. The first transistor has a first current electrode coupled to the second terminal of the first resistor, a control electrode coupled to receive a bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the second terminal of the second resistor, and a second current electrode coupled to a first power supply voltage terminal.

摘要翻译： 放大器包括放大器级和有源电感器。 放大器级具有输入端和输出端。 有源电感器包括第一和第二电阻器以及第一和第二晶体管。 第一电阻器具有耦合到放大器级的输出端的第一端子和第二端子。 第二电阻器具有耦合到放大器级的输出端的第一端子和第二端子。 第一晶体管具有耦合到第一电阻器的第二端子的第一电流电极，耦合以接收偏置电压的控制电极和第二电流电极。 第二晶体管具有耦合到第一晶体管的第二电流电极的第一电流电极，耦合到第二电阻器的第二端子的控制电极和耦合到第一电源电压端子的第二电流电极。

公开(公告)号：US20070183549A1

公开(公告)日：2007-08-09

申请号：US11349874

申请日：2006-02-08

申请人： John Angello ,  Satyavathi Akella ,  Kiyoshi Kase ,  May Len

发明人： John Angello ,  Satyavathi Akella ,  Kiyoshi Kase ,  May Len

IPC分类号： H04L25/38

CPC分类号： H04L25/38 ,  H04L7/0008

摘要： An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided. In one embodiment, the synchronous pulse occurs between successive rising edges of the clock whereas the synchronous ready signal is provided in response to the intermediate falling edge of the clock.

摘要翻译： 一种自适应可变长度脉冲同步器，包括状态保持器电路，异步脉冲沿检测电路，数据同步电路和脉冲沿同步电路。 状态保持电路检测异步脉冲的前沿。 在状态保持电路检测到前沿之后，异步脉冲沿检测电路检测异步脉冲的后沿。 在检测到异步脉冲之后，异步脉冲沿检测电路还提供与时钟信号同步的脉冲。 数据同步电路锁存异步数据，并响应于同步脉冲提供同步数据。 在提供同步数据之后，脉冲沿同步提供同步就绪信号。 在一个实施例中，同步脉冲发生在时钟的连续上升沿之间，而响应于时钟的中间下降沿提供同步就绪信号。

公开(公告)号：US20060082403A1

公开(公告)日：2006-04-20

申请号：US10967898

申请日：2004-10-18

申请人： Kiyoshi Kase

发明人： Kiyoshi Kase

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K5/1504 ,  H03K2005/00039

摘要： A circuit and a method for interpolative delay is provided. The circuit includes a delay locked loop with interpolation delay. The delay locked loop includes a differential inverter, an interpolation circuit, and a differential compare circuit. The differential inverter is coupled to receive a differential clock signal and coupled to provide an inverted differential clock signal. The interpolation circuit is coupled to receive both the clock signal and the inverted clock signal, and to provide an interpolated clock signal having a first delay relative to the clock signal. The differential compare circuit is coupled to receive the inverted clock signal and coupled to provide a non-interpolated clock signal having a second delay relative to the clock signal. The second delay corresponds to a full delay of the differential inverter and the first delay corresponds to a predetermined fraction of the full delay.

公开(公告)号：US20060071702A1

公开(公告)日：2006-04-06

申请号：US10958831

申请日：2004-10-05

申请人： Kiyoshi Kase

发明人： Kiyoshi Kase

IPC分类号： G11C5/14

CPC分类号： H02M3/07 ,  G11C5/145

摘要： A well bias module outputs a voltage used to bias the wells of transistors or other semiconductor components. The well bias module includes a feedback loop having a voltage generation module and a subthreshold leakage sense module that is operable to model the transistors or other semiconductor components so as to sense the subthreshold leakage resulting from a particular well bias voltage output by the voltage generation module. The subthreshold leakage sense module provides a representation of the sensed subthreshold leakage to the voltage generation module, which adjusts the magnitude of the well bias voltage based on this representation so as to reduce or minimize the subthreshold leakage in the transistors or other semiconductor components.

摘要翻译： 阱偏置模块输出用于偏置晶体管或其他半导体元件的阱的电压。 阱偏置模块包括具有电压产生模块和亚阈值泄漏检测模块的反馈环路，该模块可操作以对晶体管或其它半导体元件建模，以便感测由电压产生模块输出的特定阱偏置电压产生的亚阈值泄漏 。 亚阈值泄漏检测模块提供对电压产生模块的感测到的亚阈值泄漏的表示，该电压产生模块基于该表示来调整阱偏置电压的幅度，以便减小或最小化晶体管或其它半导体部件中的亚阈值泄漏。

公开(公告)号：US20060012356A1

公开(公告)日：2006-01-19

申请号：US10891811

申请日：2004-07-15

申请人： Kiyoshi Kase ,  May Len

发明人： Kiyoshi Kase ,  May Len

IPC分类号： G05F1/40

CPC分类号： G05F1/575

摘要： A voltage regulator includes a first and second amplifier stage, an output stage, and a variable zero circuit. The first amplifier stage is coupled to receive a reference voltage and introduces a first pole of the voltage regulator. The second amplifier stage is coupled to the first amplifier stage and introduces a second pole of the voltage regulator. The output stage is coupled to the second amplifier stage, has an output driver, and is coupled to provide an output voltage based on the reference voltage. The variable zero circuit is coupled to the first amplifier stage, the second amplifier stage, and the output stage. The variable zero circuit provides a zero to compensate for at least one of the first pole or the second pole of the voltage regulator based on a gate to source voltage of the output driver and a drain to source voltage of the output driver.

摘要翻译： 电压调节器包括第一和第二放大器级，输出级和可变零电路。 第一放大器级耦合以接收参考电压并引入电压调节器的第一极。 第二放大器级耦合到第一放大器级并引入电压调节器的第二极。 输出级耦合到第二放大器级，具有输出驱动器，并且被耦合以提供基于参考电压的输出电压。 可变零电路耦合到第一放大器级，第二放大级和输出级。 基于输出驱动器的栅极 - 源极电压和输出驱动器的漏极 - 源极电压，可变零电路提供零以补偿电压调节器的第一极点或第二极点中的至少一个极点。

公开(公告)号：US06707339B1

公开(公告)日：2004-03-16

申请号：US10301992

申请日：2002-11-22

申请人： Kiyoshi Kase ,  Joseph Y. Chan ,  Chunhe Zhao

发明人： Kiyoshi Kase ,  Joseph Y. Chan ,  Chunhe Zhao

IPC分类号： H03F345

CPC分类号： H03F3/3023 ,  H03F3/45183 ,  H03F2203/45454 ,  H03F2203/45584 ,  H03F2203/45658

摘要： An operational amplifier circuit (10) uses a first operational amplifier (16) to selectively provide a boosted drive current in response to an input signal voltage transitioning. The boosted driver current is used by a second operational amplifier (22) having a single high gain stage (76). The output drive current of the operational amplifier circuit (10) is increased to a predetermined maximum value for a predetermined time after an input signal transition in order to source increased current to a capacitive or inductive load only during output signal transitions. Separate current boost circuits (30, 70) in each of the first and second operational amplifiers enable early signal transition detection and ensure continuation of increased current until completion of the signal transition.

摘要翻译： 运算放大器电路（10）使用第一运算放大器（16）来响应于输入信号电压转换来选择性地提供升压的驱动电流。 升压的驱动器电流由具有单个高增益级（76）的第二运算放大器（22）使用。 运算放大器电路（10）的输出驱动电流在输入信号转换之后的预定时间内增加到预定的最大值，以便仅在输出信号转换期间将电流增加到电容或电感性负载。 第一和第二运算放大器中的每一个中的独立电流升压电路（30,70）可以实现早期的信号转换检测，并确保持续增加的电流，直到完成信号转换。

公开(公告)号：US07508246B2

公开(公告)日：2009-03-24

申请号：US11532295

申请日：2006-09-15

申请人： Kiyoshi Kase ,  Dzung T. Tran

发明人： Kiyoshi Kase ,  Dzung T. Tran

IPC分类号： H03H11/26 ,  H03B1/00 ,  H03K19/094

CPC分类号： H03H11/26

摘要： A circuit's performance may vary based on various factors such as, for example, process, voltage, and/or temperature. In one embodiment, a circuit includes an input terminal which receives an input signal, a delay selection section which delays the input signal by a delay amount selected by a performance variation indicator, an impedance selection section which outputs the delayed input signal as a compensated delayed signal, where the impedance selection section uses a driver impedance amount selected by the performance variation indicator, and an output terminal which outputs the compensated delayed signal. The circuit may also include a ring oscillator, a frequency counter which provides a count value which indicates a number of rising edges of an output of the ring oscillator which occur during a period of a reference frequency, and a decoder which uses the count value to output the performance variation indicator.

摘要翻译： 电路的性能可以基于诸如例如工艺，电压和/或温度的各种因素而变化。 在一个实施例中，电路包括接收输入信号的输入端子，延迟选择部分，其将输入信号延迟由性能变化指示器选择的延迟量;阻抗选择部分，其输出延迟的输入信号作为经补偿的延迟 信号，其中阻抗选择部分使用由性能变化指示器选择的驱动器阻抗量，以及输出端子，其输出经补偿的延迟信号。 电路还可以包括环形振荡器，频率计数器，其提供指示在参考频率的周期期间发生的环形振荡器的输出的上升沿的数量的计数值;以及解码器，其使用计数值 输出性能变化指标。

公开(公告)号：US07479813B2

公开(公告)日：2009-01-20

申请号：US11424132

申请日：2006-06-14

申请人： Kiyoshi Kase ,  Dzung T. Tran ,  May Len

发明人： Kiyoshi Kase ,  Dzung T. Tran ,  May Len

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： G05F3/205

摘要： In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.

摘要翻译： 在一种形式中，电路具有偏置级，其具有用于接收输入信号的输入信号端子。 该电路用驱动级修改输入信号以提供补码形式的输出信号。 电路的驱动级中的驱动晶体管具有连接到负载的端子和耦合到输入信号端子的控制电极的体积。 电路的偏置级中的偏置晶体管具有直接连接到负载的端子和驱动晶体管体的体积。 偏置晶体管具有耦合到输入信号端子的控制电极。 输入信号偏置驱动晶体管和偏置晶体管的体积，并降低晶体管阈值电压。 电路输出阻抗的线性提高，RF干扰降低。 还提供较低的电压操作。

公开(公告)号：US07420394B2

公开(公告)日：2008-09-02

申请号：US11561209

申请日：2006-11-17

申请人： Kiyoshi Kase ,  Dzung T. Tran

发明人： Kiyoshi Kase ,  Dzung T. Tran

IPC分类号： H03K19/094

CPC分类号： H03K3/3565

摘要： An input buffer circuit with hysteresis includes a first stage and a second stage. The first stage includes a resistive device to provide a resistance between two nodes of the first stage. The two nodes are responsive to a signal input. The second stage includes four series-coupled transistors. A first node is coupled to the control electrodes of two of the four transistors and the second node is coupled to the control electrodes of the other two transistors. The second stage includes a signal output. In some examples, a resistance provided by the resistive device is variable and provides the buffer circuit with hysteresis.

摘要翻译： 具有迟滞的输入缓冲电路包括第一级和第二级。 第一级包括用于在第一级的两个节点之间提供电阻的电阻装置。 两个节点响应信号输入。 第二级包括四个串联耦合晶体管。 第一节点耦合到四个晶体管中的两个的控制电极，并且第二节点耦合到另外两个晶体管的控制电极。 第二级包括信号输出。 在一些示例中，由电阻装置提供的电阻是可变的并且为缓冲电路提供迟滞。