利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

32 条记录 (耗时 0.018 秒)

    Phase detector circuit for clock and data recovery circuit and optical communication device having the same
    1.
    发明授权
    Phase detector circuit for clock and data recovery circuit and optical communication device having the same 失效
    用于时钟和数据恢复电路的相位检测电路和具有该相位检测电路的光通信装置

    公开(公告)号：US08483579B2

    公开(公告)日：2013-07-09

    申请号：US12538250

    申请日：2009-08-10

    申请人： Koji Fukuda

    发明人： Koji Fukuda

    IPC分类号： H04B10/06 ,  H04L7/04 ,  G01R25/00 ,  H03D13/00

    CPC分类号： H04B10/69 ,  H03D13/003 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/091 ,  H04L7/0337

    摘要： A high-accuracy phase detector circuit compatible with a 1/N rate architecture is provided. The phase detector circuit has as many as N track-and-hold circuits for tracking and holding N-phase clock signals CLK—1 to CLK_N in synchronization with a rising edge of input data signal DIN. Out of the N-phase clock signals CLK—1 to CLK_N outputted from as many track-and-hold circuits, only the one whose rising edge is most synchronized with a rising edge of the input data signal DIN is selected and outputted as a phase difference signal.

    摘要翻译： 提供了与1 / N速率架构兼容的高精度相位检测器电路。 相位检测器电路具有与输入数据信号DIN的上升沿同步地跟踪和保持N相时钟信号CLK-1至CLK_N的多达N个跟踪和保持电路。 在从多个跟踪和保持电路输出的N相时钟信号CLK-1至CLK_N中，只有上升沿与输入数据信号DIN的上升沿同步的那一个被选择并输出为相位 差分信号。

    DATA JUDGMENT/PHASE COMPARISON CIRCUIT
    2.
    发明申请
    DATA JUDGMENT/PHASE COMPARISON CIRCUIT 失效
    数据判断/相位比较电路

    公开(公告)号：US20120133394A1

    公开(公告)日：2012-05-31

    申请号：US13255902

    申请日：2009-09-29

    申请人： Koji Fukuda ,  Hiroki Yamashita

    发明人： Koji Fukuda ,  Hiroki Yamashita

    IPC分类号： H03K5/26

    CPC分类号： H03K5/26 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/033

    摘要： The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C GOOD and C BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted. Depending on a relation among data outputs of total three symbols obtained by combining a symbol and symbols previous and subsequent thereto, it is selected that either the Early or the Late is to be outputted by a decision logic EL_LOGIC.

    摘要翻译： 本发明涉及一种包括时钟产生电路的时钟发生电路和信号再现电路，更具体地说，本发明提供一种能够通过单相时钟执行数据判断和相位比较两者的数据判断/相位比较电路 并且提供包括数据判断/相位比较电路的CDR（时钟数据恢复）电路。 相同的数据和时钟被输入到两个数据判断单元C GOOD和C BAD，每个数据判断单元C GOOD和C BAD具有正确判断数据所需的不同的数据确定周期（建立/保持时间），并且具有较短的数据判断单元C GOOD的输出 将所需数据确定周期作为数据判断/相位比较电路的数据输出。 当两个数据判断单元的输出彼此不同时，输出表示时钟相位太早的信号Early，或指示时钟相位太迟的信号Late。 根据通过组合符号和先前和之后的符号获得的总共三个符号的数据输出之间的关系，选择Early或Late由判决逻辑EL_LOGIC输出。

    Clock recovery circuit
    3.
    发明授权
    Clock recovery circuit 失效
    时钟恢复电路

    公开(公告)号：US08149973B2

    公开(公告)日：2012-04-03

    申请号：US12320573

    申请日：2009-01-29

    申请人： Koji Fukuda ,  Hiroki Yamashita

    发明人： Koji Fukuda ,  Hiroki Yamashita

    IPC分类号： H04L7/00

    CPC分类号： H04L7/033 ,  H03L7/081 ,  H03L7/0812 ,  H03L7/087 ,  H04L7/027 ,  H04L7/0276 ,  H04L7/10

    摘要： A clock recovery circuit capable of simultaneously satisfying all of a bit synchronization period, a clock wander tracking performance, and a high high-frequency jitter tolerance. The clock recovery circuit includes: a phase difference detecting circuit that detects a phase difference between an input data signal and a recovery clock; an averaging circuit that averages the output of the phase difference detecting circuit; a sampling and holding circuit with resetting that samples and holds the output of the phase difference detecting circuit; and a recovery clock generating circuit that generates a recovery clock having a phase corresponding to the sum of the integral value of the output of the averaging circuit and the output of the sampling and holding circuit with resetting. The sampling and holding circuit with resetting receives a burst transmission start signal and samples and holds the output of the phase difference detecting. In addition, the sampling and holding circuit with resetting receives a burst transmission end signal and resets the held value to an initial value.

    摘要翻译： 一种时钟恢复电路，能够同时满足所有的位同步周期，时钟漂移跟踪性能和高高频抖动容限。 时钟恢复电路包括：相位差检测电路，其检测输入数据信号和恢复时钟之间的相位差; 平均电路，对所述相位差检测电路的输出进行平均; 具有采样和保持相位差检测电路的输出的复位的采样和保持电路; 以及恢复时钟发生电路，其生成具有与平均电路的输出的积分值和采样保持电路的输出的复位相对应的相位的恢复时钟。 具有复位的取样和保持电路接收脉冲串传输开始信号，采样并保持相位差检测的输出。 此外，具有复位的采样和保持电路接收突发传输结束信号，并将保持值重置为初始值。

    Pulse amplitude modulation circuit with pulse width equalization
    4.
    发明授权
    Pulse amplitude modulation circuit with pulse width equalization 失效
    脉冲幅度调制电路具有脉冲宽度均衡

    公开(公告)号：US08040776B2

    公开(公告)日：2011-10-18

    申请号：US11782705

    申请日：2007-07-25

    申请人： Koji Fukuda ,  Hidehiro Toyoda ,  Hiroki Yamashita

    发明人： Koji Fukuda ,  Hidehiro Toyoda ,  Hiroki Yamashita

    IPC分类号： G11B7/0045

    CPC分类号： G11B20/10009 ,  G11B20/10046 ,  G11B20/10194 ,  G11B20/10481 ,  G11B2220/2537

    摘要： In pulse width control equalization, attention is paid to the existence of the symmetry of anteroposterior signals and thereby the size of a table in which the adjustment amount of an edge position is stored is reduced to the power of one-half. Pattern jitters caused by inter-symbol interference are suppressed. The pulse time span of each symbol is adjusted to an optimum pulse width determined by a calculating formula or search in a table in response to a code sequence to be transmitted. In the configuration wherein a table is used, the table to store an edge position adjustment amount wherein the row of the exclusive OR of two symbols located at positions symmetrical to each other before and after a center symbol now ready to be sent in the code sequence is used as a search key is made.

    摘要翻译： 在脉冲宽度控制均衡中，注意前后信号的对称性的存在，从而将存储边缘位置的调整量的表的尺寸减小到二分之一的幂。 由符号间干扰引起的模式抖动被抑制。 每个符号的脉冲时间间隔被调整为由计算公式确定的最佳脉冲宽度或响应于要发送的代码序列在表中搜索。 在使用表格的结构中，存储边缘位置调整量的表，其中位于现在准备好以代码序列发送的中心符号之前和之后彼此对称的两个符号的异或的行 被用作搜索键。

    Tape loading mechanism for magnetic recording and/or playback equipments
    5.
    发明授权
    Tape loading mechanism for magnetic recording and/or playback equipments 失效
    用于磁记录和/或播放设备的磁带加载机构

    公开(公告)号：US4912578A

    公开(公告)日：1990-03-27

    申请号：US177470

    申请日：1988-04-01

    申请人： Noboru Katohno ,  Koji Fukuda

    发明人： Noboru Katohno ,  Koji Fukuda

    IPC分类号： G11B15/665

    CPC分类号： G11B15/6656

    摘要： In a tape loading mechanism for recording and/or playback equipment in which a magnetic tape is drawn from a cassette to be wound around a cylinder having a head at a predetermined angle, an elongated member for moving drawing members to draw the magnetic tape from the cassette is disposed and extends in a space between a rotating shaft of a cylinder motor for rotating the cylinder identical with a rotational shaft of the cylinder motor and a capstan motor for rotating a capstan shaft identical with the capstan shaft which feeds the magnetic tape together with a pinch roller.

    摘要翻译： 在用于记录和/或重放设备的磁带加载机构中，其中磁带从要被卷绕在具有头部的预定角度的圆柱体上的磁带被拉出，用于移动拉伸部件以从 磁带盒被设置并且在气缸电动机的旋转轴之间的空间中延伸，用于旋转与气缸电动机的旋转轴相同的气缸和主导轴电动机，用于使与主轴轴相同的主导轴转动，主轴轴与馈送磁带一起 一个压紧辊。

    Semiconductor integrated circuit device
    7.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07899144B2

    公开(公告)日：2011-03-01

    申请号：US11937592

    申请日：2007-11-09

    申请人： Koji Fukuda ,  Hiroki Yamashita

    发明人： Koji Fukuda ,  Hiroki Yamashita

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0337

    摘要： The present invention is to provide a semiconductor integrated circuit device provided with a sufficient margin to variations of input waveforms. For example, the semiconductor integrated circuit device is provided with a clock and data determination circuit receiving an input data signal and a clock signal and outputting a recovered data signal, a first phase comparison signal and a second phase comparison signal and a clock signal generating circuit generating the clock signal with a phase corrected based on the first phase comparison signal and the second phase comparison signal. The clock and data determination circuit latches the input data signal in synchronization with the clock signal using a plurality of thresholds as determination reference and generates two kinds of candidates composed of combination of a recovered data signal and phase comparison signals by processing a latch result. Further, one of the two kinds of candidates is selected by a selector circuit based on a symbol of a recovered data signal at a previous cycle.

    摘要翻译： 本发明提供一种半导体集成电路器件，其对输入波形的变化提供足够的余量。 例如，半导体集成电路装置具有时钟和数据判定电路，接收输入数据信号和时钟信号，并输出恢复的数据信号，第一相位比较信号和第二相位比较信号以及时钟信号发生电路 利用基于第一相位比较信号和第二相位比较信号校正的相位产生时钟信号。 时钟和数据确定电路使用多个阈值与时钟信号同步地锁存输入数据信号作为确定基准，并且通过处理锁存结果生成由恢复的数据信号和相位比较信号的组合组成的两种候选。 此外，两种候选中的一种由选择器电路基于前一周期的恢复数据信号的符号来选择。

    Logic circuit
    8.
    发明授权
    Logic circuit 失效
    逻辑电路

    公开(公告)号：US07768330B2

    公开(公告)日：2010-08-03

    申请号：US12003443

    申请日：2007-12-26

    申请人： Fumio Yuuki ,  Hiroki Yamashita ,  Masayoshi Yagyu ,  Koji Fukuda

    发明人： Fumio Yuuki ,  Hiroki Yamashita ,  Masayoshi Yagyu ,  Koji Fukuda

    IPC分类号： H03K3/00

    CPC分类号： H03K3/356191 ,  H03K3/356139 ,  H03K3/3562 ,  H03M9/00

    摘要： For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.

    摘要翻译： 例如，在包括具有差分放大器配置的数据采集部分的逻辑电路中提供增益控制部分和公共节点控制部分，并且当点击信号为“H”电平时获取数据输入信号，并且锁存部分 当点击信号为“L”电平时，锁存来自数据采集部分的数据输出信号。 增益控制部分设置在差分放大器中的NMOS晶体管的公共节点之间，用于使高频带中差分放大器的增益高于低频带。 当时钟信号为“L”电平时，公共节点控制部分用于控制电荷，以消除公共节点之间的电位差。 因此，数据输出信号的转换时间被加速并且在锁存部分中增加了设置余量。 因此，上述技术可以加速诸如锁存电路的各种逻辑电路的操作。

    Clock recovery circuit
    9.
    发明申请
    Clock recovery circuit 失效
    时钟恢复电路

    公开(公告)号：US20090207957A1

    公开(公告)日：2009-08-20

    申请号：US12320573

    申请日：2009-01-29

    申请人： Koji Fukuda ,  Hiroki Yamashita

    发明人： Koji Fukuda ,  Hiroki Yamashita

    IPC分类号： H04L7/00

    CPC分类号： H04L7/033 ,  H03L7/081 ,  H03L7/0812 ,  H03L7/087 ,  H04L7/027 ,  H04L7/0276 ,  H04L7/10

    摘要： A clock recovery circuit capable of simultaneously satisfying all of a bit synchronization period, a clock wander tracking performance, and a high high-frequency jitter tolerance. The clock recovery circuit includes: a phase difference detecting circuit that detects a phase difference between an input data signal and a recovery clock; an averaging circuit that averages the output of the phase difference detecting circuit; a sampling and holding circuit with resetting that samples and holds the output of the phase difference detecting circuit; and a recovery clock generating circuit that generates a recovery clock having a phase corresponding to the sum of the integral value of the output of the averaging circuit and the output of the sampling and holding circuit with resetting. The sampling and holding circuit with resetting receives a burst transmission start signal and samples and holds the output of the phase difference detecting. In addition, the sampling and holding circuit with resetting receives a burst transmission end signal and resets the held value to an initial value.

    摘要翻译： 一种时钟恢复电路，能够同时满足所有的位同步周期，时钟漂移跟踪性能和高高频抖动容限。 时钟恢复电路包括：相位差检测电路，其检测输入数据信号和恢复时钟之间的相位差; 平均电路，对所述相位差检测电路的输出进行平均; 具有采样和保持相位差检测电路的输出的复位的采样和保持电路; 以及恢复时钟产生电路，其生成具有与平均电路的输出的积分值和采样保持电路的输出的复位相对应的相位的恢复时钟。 具有复位的取样和保持电路接收脉冲串传输开始信号，采样并保持相位差检测的输出。 此外，具有复位的采样和保持电路接收突发传输结束信号，并将保持值重置为初始值。

    Logic circuit
    10.
    发明申请
    Logic circuit 失效
    逻辑电路

    公开(公告)号：US20080204100A1

    公开(公告)日：2008-08-28

    申请号：US12003443

    申请日：2007-12-26

    申请人： Fumio Yuuki ,  Hiroki Yamashita ,  Masayoshi Yagyu ,  Koji Fukuda

    发明人： Fumio Yuuki ,  Hiroki Yamashita ,  Masayoshi Yagyu ,  Koji Fukuda

    IPC分类号： H03K3/289 ,  H03K3/286

    CPC分类号： H03K3/356191 ,  H03K3/356139 ,  H03K3/3562 ,  H03M9/00

    摘要： For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.

    摘要翻译： 例如，在包括具有差分放大器配置的数据采集部分的逻辑电路中提供增益控制部分和公共节点控制部分，并且当点击信号为“H”电平时获取数据输入信号，并且锁存部分 当点击信号为“L”电平时，锁存来自数据采集部分的数据输出信号。 增益控制部分设置在差分放大器中的NMOS晶体管的公共节点之间，用于使高频带中差分放大器的增益高于低频带。 当时钟信号为“L”电平时，公共节点控制部分用于控制电荷，以消除公共节点之间的电位差。 因此，数据输出信号的转换时间被加速并且在锁存部分中增加了设置余量。 因此，上述技术可以加速诸如锁存电路的各种逻辑电路的操作。