公开(公告)号：US08471736B1

公开(公告)日：2013-06-25

申请号：US13441723

申请日：2012-04-06

申请人： Richard W. D. Booth ,  Koji Takinami

发明人： Richard W. D. Booth ,  Koji Takinami

IPC分类号： H03M1/48

CPC分类号： G04F10/005

摘要： An automatically calibrating time to digital conversion circuit. The circuit includes a first circuit node for switchably receiving a first calibration signal and a second circuit node coupled with the first circuit node via a first delay path. A third circuit node for switchably receiving a second calibration signal the same as the first calibration signal is coupled with a fourth circuit node via a second delay path. A calibration portion has a third delay path switchably connected with the fourth circuit node and a fourth delay path switchably connected with the second circuit node. The calibration portion generates a delay adjustment signal for adjusting a time delay of the first delay path such that the first time delay combined with the fourth time delay equals the second time delay combined with the third time delay. The calibration portion is disconnected when calibration is not desired for conserving power.

摘要翻译： 自动校准时间到数字转换电路。 电路包括用于可转换地接收第一校准信号的第一电路节点和经由第一延迟路径与第一电路节点耦合的第二电路节点。 用于可切换地接收与第一校准信号相同的第二校准信号的第三电路节点经由第二延迟路径与第四电路节点耦合。 校准部分具有可切换地与第四电路节点连接的第三延迟路径和与第二电路节点可切换地连接的第四延迟路径。 校准部分产生用于调整第一延迟路径的时间延迟的延迟调整信号，使得与第四时间延迟相结合的第一时间延迟等于与第三时间延迟相结合的第二时间延迟。 当不需要校准以节省电力时，校准部分断开。

公开(公告)号：US08222939B2

公开(公告)日：2012-07-17

申请号：US12838754

申请日：2010-07-19

申请人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

发明人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

IPC分类号： H03L7/06

CPC分类号： H03L7/16 ,  H03L2207/50

摘要： The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches.

摘要翻译： 本发明涉及一种全数字锁相环中毛刺校正的方法和系统。 全数字锁相环可以包括相位误差信号生成单元，多相位振荡器，毛刺校正单元和相位数字转换器。 相数转换器从多相振荡器接收多相信号并产生相位信号。 误差信号发生单元接收相位信号和参考相位信号，并产生馈送到毛刺校正单元的相位误差信号。 毛刺校正单元通过相位误差信号的一部分去除相位误差信号中的毛刺。 锁相环还可以包括相位旋转器和校准块。 校准块指示相位旋转器通过相位旋转旋转多相信号，该相位旋转产生最小数量的毛刺。

公开(公告)号：US20110018640A1

公开(公告)日：2011-01-27

申请号：US12508464

申请日：2009-07-23

申请人： Paul Cheng-Po Liang ,  Koji Takinami ,  Toru Matsuura

发明人： Paul Cheng-Po Liang ,  Koji Takinami ,  Toru Matsuura

IPC分类号： H03F1/00

CPC分类号： H03F1/0227 ,  H03F1/02 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2200/351 ,  H04B2001/045

摘要： A broad power band transmitter utilizing a duty cycle modulator achieves 80dB of power range for 3G signals. The present invention greatly improves the efficiency of transmitters used in mobile phones, for example, by using the duty cycle modulator during medium and low power levels of the transmitting power amplifier. The power amplifier operates in three different modes based upon the amplifier power level selected. The power amplifier operates in an EER mode during high power levels, in a DCM ERR mode during medium power levels, and in a DCM mode during low power levels.

摘要翻译： 利用占空比调制器的宽带功率带发射机实现3G信号的80dB的功率范围。 本发明大大提高了在移动电话中使用的发射机的效率，例如通过在发射功率放大器的中等和低功率电平期间使用占空比调制器。 功率放大器基于选择的放大器功率电平在三种不同的模式下工作。 功率放大器在高功率电平下处于EER模式，在中等功率电平下处于DCM ERR模式，在低功率级下处于DCM模式。

公开(公告)号：US20100015932A1

公开(公告)日：2010-01-21

申请号：US12176570

申请日：2008-07-21

申请人： Paul Cheng-Po Liang ,  Koji Takinami

发明人： Paul Cheng-Po Liang ,  Koji Takinami

IPC分类号： H04B1/66

CPC分类号： H04B1/66

摘要： A multi-mode communications transmitter includes a signal decomposer that converts rectangular-coordinate in-channel and quadrature channel signals into polar-coordinate amplitude and angle component signals and form therefrom first and second modulation signals. The signal decomposition process performed by the signal decomposer combines envelope-reduction and restoration (ERR) with filtering to reduce the bandwidths of the first and second modulation signals compared to the bandwidths of the unmodified amplitude and angle component signals. The reduction in signal bandwidths eases the design requirements of the electrical components needed to process and generate the signals applied to the power supply and radio frequency (RF) input ports of the multi-mode communications transmitter's power amplifier (PA). It also makes the multi-mode communications transmitter more forgiving to gain and delay mismatches between the signals applied to the power supply and RF input ports of the PA, compared to conventional polar modulation transmitters.

摘要翻译： 多模式通信发射机包括信号分解器，其将矩形坐标的信道内和正交信道信号转换为极坐标振幅和角度分量信号，并从其形成第一和第二调制信号。 由信号分解器进行的信号分解处理将包络减少和恢复（ERR）与滤波相结合，以与未修改的幅度和角度分量信号的带宽相比降低第一和第二调制信号的带宽。 信号带宽的减少可以减轻处理和产生施加到多模式通信发射机功率放大器（PA）的电源和射频（RF）输入端口的信号所需的电气部件的设计要求。 与传统的极性调制发射机相比，它还使得多模式通信发射机更加宽容地获得并延迟了施加到PA的电源和RF输入端口的信号之间的不匹配。

公开(公告)号：US20050190002A1

公开(公告)日：2005-09-01

申请号：US10676654

申请日：2003-10-01

申请人： Koji Takinami ,  Hisashi Adachi ,  Tokio Endoh

发明人： Koji Takinami ,  Hisashi Adachi ,  Tokio Endoh

IPC分类号： H03B1/00 ,  H03B5/00 ,  H03B5/12 ,  H03B7/06 ,  H03C3/22 ,  H04B1/16

CPC分类号： H03B5/1215 ,  H03B5/1228 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1293 ,  H03B2201/025 ,  H03L7/099

摘要： A voltage-controlled oscillator having an inductor circuit, n pieces (n is two or more) of variable capacitance circuit having variable capacitance elements, negative resistance circuits, and reference voltage generation means of generating a reference voltage from a power supply voltage, and wherein a predetermined reference voltage is inputted to some terminals of the variable capacitance elements of the n pieces of variable capacitance circuit, a control voltage is inputted to the other terminals thereof, and of the variable capacitance elements of the n pieces of variable capacitance circuits, the predetermined reference voltage inputted to some terminals of the variable capacitance elements of at least two pieces of the variable capacitance circuit is different.

摘要翻译： 一种具有电感电路的压控振荡器，具有可变电容元件的可变电容电路的n个（n为2个以上），负电阻电路和从电源电压生成基准电压的基准电压生成单元，其中， 将预定的参考电压输入到n个可变电容电路的可变电容元件的一些端子，将一个控制电压输入到其它端子，以及n个可变电容电路的可变电容元件， 输入至少两个可变电容电路的可变电容元件的一些端子的预定参考电压是不同的。

公开(公告)号：US08489046B2

公开(公告)日：2013-07-16

申请号：US12176570

申请日：2008-07-21

申请人： Paul Cheng-Po Liang ,  Koji Takinami

发明人： Paul Cheng-Po Liang ,  Koji Takinami

IPC分类号： H01Q11/12 ,  H04B1/04

CPC分类号： H04B1/66

摘要： A multi-mode communications transmitter includes a signal decomposer that converts rectangular-coordinate in-channel and quadrature channel signals into polar-coordinate amplitude and angle component signals and form therefrom first and second modulation signals. The signal decomposition process performed by the signal decomposer combines envelope-reduction and restoration (ERR) with filtering to reduce the bandwidths of the first and second modulation signals compared to the bandwidths of the unmodified amplitude and angle component signals. The reduction in signal bandwidths eases the design requirements of the electrical components needed to process and generate the signals applied to the power supply and radio frequency (RF) input ports of the multi-mode communications transmitter's power amplifier (PA). It also makes the multi-mode communications transmitter more forgiving to gain and delay mismatches between the signals applied to the power supply and RF input ports of the PA, compared to conventional polar modulation transmitters.

摘要翻译： 多模式通信发射机包括信号分解器，其将矩形坐标的信道内和正交信道信号转换为极坐标振幅和角度分量信号，并从其形成第一和第二调制信号。 由信号分解器进行的信号分解处理将包络减少和恢复（ERR）与滤波相结合，以与未修改的幅度和角度分量信号的带宽相比降低第一和第二调制信号的带宽。 信号带宽的减少可以减轻处理和产生施加到多模式通信发射机功率放大器（PA）的电源和射频（RF）输入端口的信号所需的电气部件的设计要求。 与传统的极性调制发射机相比，它还使得多模式通信发射机更加宽容地获得并延迟了施加到PA的电源和RF输入端口的信号之间的不匹配。

公开(公告)号：US08340209B2

公开(公告)日：2012-12-25

申请号：US12554863

申请日：2009-09-04

申请人： Paul Cheng-Po Liang ,  Koji Takinami ,  Hua Wang ,  Toru Matsuura

发明人： Paul Cheng-Po Liang ,  Koji Takinami ,  Hua Wang ,  Toru Matsuura

IPC分类号： H04L25/34 ,  H04L25/49

CPC分类号： H04L25/4917

摘要： The disclosure relates to a method and apparatus for providing efficient signal transmission. Conventional linear amplifiers are most efficient when operated in compressed mode. In the compressed mode, the digital power amplifier switches between the on and off modes. A digital power amplifier operates in compressed mode only if the incoming signal is an on-off constant envelop signal. In one embodiment, the disclosure provides a method and apparatus for converting a digital baseband signal to on-off constant envelop signals for processing through binary-weighted or thermometer-weighted amplifier which are operated in compressed mode.

摘要翻译： 本公开涉及一种用于提供有效信号传输的方法和装置。 传统的线性放大器在压缩模式下工作时效率最高。 在压缩模式下，数字功率放大器在导通和关断模式之间切换。 数字功率放大器仅在输入信号为开 - 关恒定包络信号时才以压缩模式工作。 在一个实施例中，本公开提供了一种用于将数字基带信号转换为开 - 关恒定包络信号以便通过以压缩模式操作的二进制加权或温度计加权放大器进行处理的方法和装置。

公开(公告)号：US08193870B2

公开(公告)日：2012-06-05

申请号：US12838820

申请日：2010-07-19

申请人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

发明人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

IPC分类号： H03B7/12

CPC分类号： H03L7/0995 ,  H03L2207/06 ,  H03L2207/50

摘要： The present invention is a method and system for compensation of frequency pulling in an all digital phase lock loop. The all digital phase lock loop can utilize a multi-phase oscillator including latches with substantially all of the latches paired with a corresponding dummy cell. The dummy cells can have impedance characteristics, such as variable capacitance values which correspond to the variable capacitance value of the latches such that the sum of the two variable capacitance values remains substantially constant, even when the polarity of the reference clock signal changes. The dummy cells can be, for example, variable capacitors or dummy latches. The phase lock loop can also include a multiplying unit. The multiplying unit can receive a reference clock signal and generate a frequency multiplied reference clock signal.

摘要翻译： 本发明是用于补偿全数字锁相环中的频率牵引的方法和系统。 所有数字锁相环可以利用多相振荡器，其包括基本上所有锁存器与相应的虚拟单元配对的锁存器。 虚拟单元可以具有阻抗特性，例如对应于锁存器的可变电容值的可变电容值，使得即使参考时钟信号的极性改变，两个可变电容值的总和也保持基本恒定。 虚拟单元可以是例如可变电容器或虚拟锁存器。 锁相环也可以包括乘法单元。 乘法单元可以接收参考时钟信号并产生倍频参考时钟信号。

公开(公告)号：US20120013407A1

公开(公告)日：2012-01-19

申请号：US12838820

申请日：2010-07-19

申请人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

发明人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

IPC分类号： H03L7/00 ,  H03B19/14

CPC分类号： H03L7/0995 ,  H03L2207/06 ,  H03L2207/50

摘要： The present invention is a method and system for compensation of frequency pulling in an all digital phase lock loop. The all digital phase lock loop can utilize a multi-phase oscillator including latches with substantially all of the latches paired with a corresponding dummy cell. The dummy cells can have impedance characteristics, such as variable capacitance values which correspond to the variable capacitance value of the latches such that the sum of the two variable capacitance values remains substantially constant, even when the polarity of the reference clock signal changes. The dummy cells can be, for example, variable capacitors or dummy latches. The phase lock loop can also include a multiplying unit. The multiplying unit can receive a reference clock signal and generate a frequency multiplied reference clock signal.

摘要翻译： 本发明是用于补偿全数字锁相环中的频率牵引的方法和系统。 所有数字锁相环可以利用多相振荡器，其包括基本上所有锁存器与相应的虚拟单元配对的锁存器。 虚拟单元可以具有阻抗特性，例如对应于锁存器的可变电容值的可变电容值，使得即使参考时钟信号的极性改变，两个可变电容值的总和也保持基本恒定。 虚拟单元可以是例如可变电容器或虚拟锁存器。 锁相环也可以包括乘法单元。 乘法单元可以接收参考时钟信号并产生倍频参考时钟信号。

公开(公告)号：US20100069025A1

公开(公告)日：2010-03-18

申请号：US12209981

申请日：2008-09-12

申请人： Koji Takinami ,  Paul Cheng-Po Liang

发明人： Koji Takinami ,  Paul Cheng-Po Liang

IPC分类号： H04B1/04

CPC分类号： H04B1/0458 ,  H03F1/0222 ,  H03F3/19 ,  H03F3/211 ,  H03F3/24 ,  H03F2200/451 ,  H03F2200/541 ,  H03G3/3042 ,  H04B1/0475

摘要： A transmitter generates first and second constant-envelope radio frequency (RF) component signals having first and second phase angles. The first and second phases are controlled by a phase controller. First and second nonlinear power amplifiers (PAs) are modulated by an amplitude-modulated power supply signal as the first and second constant-envelope RF component signals are amplified. The phase controller controls the first and second phases of the first and second constant-envelope RF component signals, in response to a power control signal, and, in so doing, controls an effective load impedance seen at the outputs of the first and second nonlinear PAs. By controlling the effective load impedance in response to a power control signal, rather than in response to rapid amplitude variations in an input signal envelope, the output power of the transmitter is efficiently controlled over a wide dynamic range even at low output powers.

摘要翻译： 发射机产生具有第一和第二相位角的第一和第二恒定包络射频（RF）分量信号。 第一和第二相由相位控制器控制。 当第一和第二恒定包络RF分量信号被放大时，第一和第二非线性功率放大器（PA）由幅度调制电源信号调制。 相位控制器响应于功率控制信号控制第一和第二恒定包络RF分量信号的第一和第二相位，并且这样做控制在第一和第二非线性信号的输出处看到的有效负载阻抗 PA。 通过响应于功率控制信号控制有效负载阻抗，而不是响应于输入信号包络中的快速幅度变化，即使在低输出功率下，发射机的输出功率也能在宽动态范围内被有效地控制。