公开(公告)号：US07126889B2

公开(公告)日：2006-10-24

申请号：US10314821

申请日：2002-12-09

申请人： Koyu Yamanoi ,  Hironobu Murata ,  Aoe Takashi

发明人： Koyu Yamanoi ,  Hironobu Murata ,  Aoe Takashi

IPC分类号： G11B7/00

CPC分类号： G11B7/131 ,  G11B7/0901 ,  G11B7/0903 ,  G11B7/0943

摘要： A circuit to improve the SN characteristic of a tracking error signal. This tracking error detection circuit is formed as a push-pull system utilizing a quadrant type photo-detector and provided with 4 gain control amplifiers 20, 22, 24, and 26, 4 bottom envelope circuits 28, 30, 32, and 34, a pair of subtracting circuits 36 and 38, adding (subtracting) circuit 40, offset circuit 42, and gain control circuit 44. Bottom envelope circuits 28, 30, 32, and 34 are configured with a capacitor-type peak-hold circuit, for example, whereby bottom envelopes of RF signals SA, SB, SC, and SD given from light receiving areas A, B, C, and D of a photo-detector via gain control amplifiers 20, 22, 24, and 26 are detected, and bottom envelope signals SAbtm, SBbtm, SCbtm, and SDbtm representing the waveforms of the respective bottom envelopes are output.

摘要翻译： 一种提高跟踪误差信号的SN特性的电路。 该跟踪误差检测电路形成为利用象限型光检测器并具有4个增益控制放大器20,22,24和26,4个底包络电路28,30,32和34的推挽系统， 一对减法电路36和38，添加（减）电路40，偏移电路42和增益控制电路44.底包络电路28,30,32和34由电容器型峰保持电路构成，例如 ，由此检测通过增益控制放大器20,22,24和26从光电检测器的光接收区域A，B，C和D给出的RF信号SA，SB，SC和SD的底部信封，并且底部 输出表示相应底部信封的波形的包络信号SAbtm，SBbtm，SCbtm和SDbtm。

公开(公告)号：US6067335A

公开(公告)日：2000-05-23

申请号：US691353

申请日：1996-08-02

申请人： Koyu Yamanoi ,  Toshio Yamauchi ,  Hiroshi Kobayashi

发明人： Koyu Yamanoi ,  Toshio Yamauchi ,  Hiroshi Kobayashi

IPC分类号： G11B20/14 ,  H03L7/07 ,  H03L7/089 ,  H03L7/22 ,  H04L7/033

CPC分类号： H03L7/0805 ,  G11B20/1403 ,  H03L7/07 ,  H03L7/0891

摘要： The present invention discloses a fully integrated data synchronization circuit for a disk drive read channel system. The data synchronization system comprises dual data synchronizers to provide read reference clocks. Dual PLL circuits are coupled to the data synchronizers to provide a stable reference frequency to data synchronizers. One of the two data synchronizers is used to obtain leading edge data, while the other is for trailing edge data. Each PLL circuit comprises a phase detector, a charge pump, and a VCO. A loop filter is used in conjunction with a charge pump to control loop characteristics of the PLLs. In an idle mode, one of the PLLs is used as a time base generator to provide a stable reference frequency to data synchronizers. Once data synchronizers achieve lock using the stable reference frequency and switch over to read data, the time base generator PLL is switched over to function as a data synchronizer PLL in a read mode. Thus, one of the PLLs is used as both time base generator and data synchronizer PLL, thereby eliminating the need for extra PLL circuitry and requiring only two PLL circuits to support time base generation and data synchronization.

摘要翻译： 本发明公开了一种用于磁盘驱动器读通道系统的完全集成的数据同步电路。 数据同步系统包括双数据同步器，以提供读取参考时钟。 双PLL电路耦合到数据同步器，为数据同步器提供稳定的参考频率。 两个数据同步器中的一个用于获取前沿数据，而另一个用于后沿数据。 每个PLL电路包括相位检测器，电荷泵和VCO。 环路滤波器与电荷泵结合使用以控制PLL的环路特性。 在空闲模式中，其中一个PLL用作时基发生器，以向数据同步器提供稳定的参考频率。 一旦数据同步器使用稳定的参考频率实现锁定并切换到读取数据，则时基发生器PLL被切换以在读取模式下用作数据同步器PLL。 因此，其中一个PLL被用作时基发生器和数据同步器PLL两者，从而不需要额外的PLL电路，并且仅需要两个PLL电路来支持时基生成和数据同步。

公开(公告)号：US20130008022A1

公开(公告)日：2013-01-10

申请号：US13245955

申请日：2011-09-27

申请人： Ming gao YAO ,  Koyu Yamanoi ,  Wei Xiong

发明人： Ming gao YAO ,  Koyu Yamanoi ,  Wei Xiong

IPC分类号： G01R1/20 ,  H05K3/10 ,  H05K3/36

CPC分类号： G01R33/09 ,  G01R15/205 ,  G01R33/091 ,  H05K1/182 ,  H05K2201/10151 ,  Y10T29/49126

摘要： An electrical current sensor device includes a first printed circuit board assembly, a second printed circuit board assembly positioned opposite to the first printed circuit board assembly, and a holder holding the first and second printed circuit board assemblies and providing a passage to allow an electrical conductor to pass through. The first printed circuit board assembly includes a first sensing circuit having a first element pair that includes two magnetoresistive elements with a first pinning direction, the second printed circuit board assembly comprises a second sensing circuit with a second element pair that includes having two magnetoresistive elements with a second pinning direction that is opposite to the first pinning direction, and the first and second pinning directions are perpendicular to a current direction of a current passing through the electrical conductor, the first sensing circuit electrically connects with the second sensing circuit to form a Wheatstone bridge circuit.

摘要翻译： 电流传感器装置包括第一印刷电路板组件，与第一印刷电路板组件相对定位的第二印刷电路板组件，以及保持第一和第二印刷电路板组件并提供通道以允许电导体 通过 第一印刷电路板组件包括具有第一元件对的第一感测电路，第一元件对包括具有第一钉扎方向的两个磁阻元件，第二印刷电路板组件包括具有第二元件对的第二感测电路，第二元件对包括具有两个磁阻元件， 与第一钉扎方向相反的第二钉扎方向，并且第一和第二钉扎方向垂直于通过电导体的电流的电流方向，第一感测电路与第二感测电路电连接以形成惠斯通 桥电路。

公开(公告)号：US20110019310A1

公开(公告)日：2011-01-27

申请号：US12458843

申请日：2009-07-23

申请人： Minggao Yao ,  Koyu Yamanoi

发明人： Minggao Yao ,  Koyu Yamanoi

IPC分类号： G11B5/60

CPC分类号： G11B5/4853

摘要： A HGA comprises a slider and a suspension with a flexure having a tongue region for supporting the slider. A read/write transducer and a piezoelectric element are formed oppositely. The connecting points of the curve beams and the inner tongue of the tongue region are in mirror positions to a center point of the inner tongue, and the connecting points of each curve beam are located at opposite sides of a center axis of the flexure. The slider has multiple electrical pads electrically connecting with the read/write transducer. The inner tongue has multiple electrical pads. The flexure has multiple inner leads electrically connected with the electrical pads of the inner tongue formed on the curve beams. The structure of the HGA prevents the read/write transducer from damaged and cause the manufacture of the HGA simpler. The present invention also discloses a suspension and a disk drive unit.

摘要翻译： HGA包括滑块和具有弯曲部的悬架，所述弯曲部具有用于支撑滑块的舌部区域。 读/写换能器和压电元件相对地形成。 弯曲梁和舌部内舌的连接点处于内舌的中心点的反射镜位置，每条曲线梁的连接点位于弯曲部的中心轴的相对侧。 滑块具有与读/写换能器电连接的多个电垫。 内舌具有多个电垫。 弯曲部具有多个内部引线，电连接于弯曲梁上形成的内部舌片的电焊盘。 HGA的结构防止读/写传感器损坏，并使HGA的制造更简单。 本发明还公开了一种悬架和盘驱动单元。

公开(公告)号：US07139229B2

公开(公告)日：2006-11-21

申请号：US10085742

申请日：2002-02-26

申请人： Koyu Yamanoi ,  Toshio Yamauchi ,  Hironobu Murata

发明人： Koyu Yamanoi ,  Toshio Yamauchi ,  Hironobu Murata

IPC分类号： G11B7/00

CPC分类号： G11B7/08511 ,  G11B2007/0006

摘要： The present invention offers an optical disk determination circuit that can improve the stability of the operation to detect the peak (pulse signal) of the received light signal, and that can improve the stability of the optical disk determination operation. When determining the type of optical disk corresponding to the depth from the surface of the plane on which a light beam is irradiated to the data recording layer, light is irradiated while varying the focal position of the light beam at a constant velocity in one direction of the depth direction from the surface of the optical disk. The bottom level of the received light signal corresponding to the intensity of this reflected light is clamped at a specified level by the bottom clamp circuit 43. The received light signal with the bottom level clamped is compared with a specified reference voltage Vref by the comparator 45, and the received light signal peak (pulse signal) is detected corresponding to the results of this comparison. The type of optical disk is determined by measuring the difference in this peak (pulse signal) detection time.

摘要翻译： 本发明提供一种光盘确定电路，其可以提高检测接收光信号的峰值（脉冲信号）的操作的稳定性，并且可以提高光盘确定操作的稳定性。 当确定与从其上照射有光束的平面的表面相对应的光盘类型到数据记录层时，照射光，同时以恒定速度在一个方向上改变光束的焦点位置 从光盘表面的深度方向。 对应于该反射光的强度的接收光信号的底部电平被底部钳位电路43钳位在指定电平。 通过比较器45将接收到的底电平的接收光信号与指定的参考电压Vref进行比较，并且根据该比较的结果检测接收到的光信号峰值（脉冲信号）。 通过测量该峰值（脉冲信号）检测时间的差异来确定光盘的类型。

公开(公告)号：US4802168A

公开(公告)日：1989-01-31

申请号：US11175

申请日：1987-02-05

申请人： Koyu Yamanoi ,  Yoshio Yoshizakiya ,  Masayoshi Dehara

发明人： Koyu Yamanoi ,  Yoshio Yoshizakiya ,  Masayoshi Dehara

IPC分类号： G01R31/319 ,  G06F3/04

CPC分类号： G01R31/3191 ,  G01R31/31928

摘要： A test signal generating circuit for generating a test signal for testing logic circuits comprises four delay units each including a setting circuitry for setting a delay time, a gate and a counter for counting clock pulses in number corresponding to the delay time placed in the setting circuitry. The output signals of two delay units are applied to a flip-flop as set input signals, while the output signals of the other two delay units are applied to the flip-flop as reset input signals, whereby the timing and/or waveform of the test signal outputted by the flip-flop is varied in dependence on the values placed in the setting circuitries.

摘要翻译： 用于产生用于测试逻辑电路的测试信号的测试信号产生电路包括四个延迟单元，每个延迟单元包括用于设置延迟时间的设置电路，用于计数对应于设置电路中的延迟时间的数量的时钟脉冲的门和计数器 。 两个延迟单元的输出信号作为设置的输入信号施加到触发器，而另外两个延迟单元的输出信号作为复位输入信号施加到触发器，由此，定时和/或波形 触发器输出的测试信号根据设置电路中的值而变化。

公开(公告)号：US4758738A

公开(公告)日：1988-07-19

申请号：US45098

申请日：1987-05-01

申请人： Koyu Yamanoi ,  Yoshio Yoshizakiya

发明人： Koyu Yamanoi ,  Yoshio Yoshizakiya

IPC分类号： G01R31/28 ,  H03K5/135 ,  H03K5/13

CPC分类号： H03K5/135

摘要： A timing signal generating apparatus comprises a first shift register having an input supplied with a first select signal and shifting the first select signal with a first reference clock signal, a second shift register having an input supplied with timing data for shifting the timing data with the first reference clock signal, a first selector having an input supplied with the output of the first shift register and extracting the output from the first shift register at a position corresponding to the stage designated by a second select signal, a second selector having an input supplied with the output of the second shift register for producing the output from the second shift register at a position corresponding to the stage designated by the second select signal, a gate circuit having inputs supplied with a second reference clock signal delayed in phase relative to the first reference clock and the output of the first selector, respectively, a counter for counting a clock signal of a repetition period shorter than that of the first reference clock signal, the counter being reset in response to the output of the gate circuit, a setting circuit having an address input supplied with the output of the second selector, an inhibit signal generating circuit having an input supplied with the second select signal, and a coincidence detection circuit having inputs supplied with the output of the counter, the output of the inhibit signal generating circuit and the output of the setting circuit, respectively. The coincidence detection circuit responds to the output of the inhibit signal generating circuit to be inhibited from producing the output for the period during which the second select signal is changed over. The timing signal derived from the coincidence detection circuit is delayed for a time equal to a sum resulting from the addition of the period of the reference clock signal multiplied with the stage number of the shift registers and a value set at the setting circuit.

公开(公告)号：US07057982B2

公开(公告)日：2006-06-06

申请号：US10340092

申请日：2003-01-10

申请人： Takashi Aoe ,  Hironobu Murata ,  Koyu Yamanoi

发明人： Takashi Aoe ,  Hironobu Murata ,  Koyu Yamanoi

IPC分类号： G11B7/00

CPC分类号： G11B7/131 ,  G11B7/0903 ,  G11B7/0909 ,  G11B7/094 ,  G11B7/0941

摘要： A servo error detector usable in an optical disk system is provided. An envelope detecting unit (24) detects the top envelopes and bottom envelopes of RF signals SA–SH, and top envelope signals SAtop–SHtop and bottom envelope signals SAbtm–SHbtm that represent the top envelope waveforms and bottom envelope waveforms of RF signals output from an optical detector. An analog/digital conversion unit (26) converts analog top envelope signals SAtop–SHtop and bottom envelope signals SAbtm–SHbtm corresponding to all input RF signals SA–SH to digital top envelope signals QAtop–QHtop and bottom envelope signals QAbtm–QHbtm, respectively. A digital operation unit (28) performs digital operation treatment for digital top envelope signals QAtop–QHtop and bottom envelope signals QAbtm–QHbtm to generate various servo error signals.

摘要翻译： 提供可用于光盘系统的伺服误差检测器。 信封检测单元（24）检测RF信号SA-SH的顶部信封和底部信封，以及顶部包络信号SAtop-SHtop和底部包络信号SAbtm-SHbtm，其表示从...输出的RF信号的顶部包络波形和底部包络波形 光学检测器。 模拟/数字转换单元（26）将对应于所有输入RF信号SA-SH的模拟顶包络信号SAtop-SHtop和底包络信号SAbtm-SHbtm分别转换为数字顶包络信号QAtop-QHtop和底包络信号QAbtm-QHbtm 。 数字操作单元（28）对数字顶包络信号QAtop-QHtop和底包络信号QAbtm-QHbtm执行数字操作处理，以产生各种伺服误差信号。

公开(公告)号：US07006423B2

公开(公告)日：2006-02-28

申请号：US10705002

申请日：2003-11-10

申请人： Koyu Yamanoi ,  Eiichi Saiki

发明人： Koyu Yamanoi ,  Eiichi Saiki

IPC分类号： G11B5/09 ,  H03F3/00

CPC分类号： G11B27/24 ,  G11B7/0053 ,  G11B7/24082 ,  G11B2220/216 ,  G11B2220/218 ,  G11B2220/2562 ,  G11B2220/2575

摘要： A mark detecting circuit that stably and reliably detects the marks for address information from an optical disk having tracks formed in a spiral shape and having waviness with a fixed period. In the land pre-pit signal extracting portion 12, by means of first bottom envelope circuit 32 with a high tracking speed, first bottom envelope signal Sbtm1 that represents at high sensitivity the bottom envelope of push-pull signal (SA+SB)−(SC+SD) is generated; and, by means of second bottom envelope circuit 34 with a low tracking speed, second bottom envelope signal Sbtm2 that represents at low sensitivity the bottom envelope waveform of push-pull signal (SA+SB)−(SC+SD) is generated. Then, with the signal, obtained by level shift treatment of said second bottom envelope signal Sbtm2 using offset circuit 36, used as threshold signal Sref, first bottom envelope signal Sbtm1 is converted to a binary form. And land pre-pit signal SLPP is extracted from push-pull signal (SA+SB)−(SC+SD).

摘要翻译： 一种标记检测电路，其从具有螺旋形状的轨道的光盘中稳定可靠地检测地址信息的标记，并且具有固定周期的波纹。 在地面预制坑信号提取部分12中，借助于具有高跟踪速度的第一底包络电路32，以高灵敏度表示推挽的底部包络线的第一底包络信号S btm1 < 产生信号（S SUB + S B B） - （S S + S D D）; 并且借助于具有低跟踪速度的第二底包络电路34，以低灵敏度表示推挽信号的底包络波形（S A> A < / SUB> + S B） - （S + C + S）D）。 然后，使用用作阈值信号S ref，ref的第一底包络信号S，通过使用偏移电路36的所述第二底包络线信号S Btm2 <>的电平移位处理获得的信号， btm1 转换为二进制形式。 并且从推挽信号（S SUB> + S B B） - （S C）中提取地面预制坑信号S LPP + S D D）。

公开(公告)号：US06982941B2

公开(公告)日：2006-01-03

申请号：US10072100

申请日：2002-02-08

申请人： Koyu Yamanoi ,  Hironobu Murata ,  Toshio Yamauchi

发明人： Koyu Yamanoi ,  Hironobu Murata ,  Toshio Yamauchi

IPC分类号： G11B7/09

CPC分类号： G11B7/08541

摘要： An amplitude variation detection circuit that can reliably detect the mirror portion independently of the type of optical recording medium, as well as a type of information regenerating apparatus that contains said amplitude variation detecting circuit. Voltage division of top envelope signal Ste and bottom-hold signal Sbh of RF signal Srf is performed by voltage divider (16); then, after amplification by gain control amplifier (19) with a gain that corresponds to the type of optical disc (1), a prescribed offset is added by offset circuit (22) to the signal, and the resulting signal is input as mirror detection threshold signal Smt to comparator (24). The high-frequency noise component of bottom envelope signal Sbe of RF signal Srf is removed by low-pass filter (21); after amplification by gain control amplifier (20) with a gain that corresponds to the type of optical disc (1), the signal is input to comparator (24). Depending on the result of the comparison of the level of said amplified bottom envelope signal S4 with that of mirror detection threshold signal Smt, mirror detection signal Sm is generated.

摘要翻译： 可以独立于光记录介质的类型可靠地检测镜面部分的振幅变化检测电路以及包含所述振幅变化检测电路的信息再生装置的种类。 RF信号Srf的顶包络信号Ste和底部保持信号Sbh的分压由分压器（16）进行; 然后，在通过增益控制放大器（19）放大了具有对应于光盘（1）的类型的增益后，偏移电路（22）将规定的偏移量加到该信号上，并将所得到的信号作为镜像检测输入 阈值信号Smt到比较器（24）。 通过低通滤波器（21）去除RF信号Srf的底包络信号Sbe的高频噪声分量; 在通过增益控制放大器（20）放大后，其增益对应于光盘（1）的类型，该信号被输入到比较器（24）。 根据所述放大的底包络信号S 4的电平与镜检测阈值信号Smt的电平的比较的结果，产生镜像检测信号Sm。