公开(公告)号：US20050155002A1

公开(公告)日：2005-07-14

申请号：US10995658

申请日：2004-11-22

Applicant: Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

Inventor： Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/504

Abstract: An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuit are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.

Abstract translation: 等价检查方法提供第一和第二逻辑功能。 不要在第一和第二逻辑功能中插入无门的条件。 无关门的插入产生第一中间电路和第二中间电路。 当3DC门和SDC门共存在第一和第二中间电路中时，第一中间电路的所有3DC门被传播并合并成单个3DC门。 当3DC门和SDC门共存在第一和第二中间电路中时，第二中间电路的所有3DC门都被传播并合并成单个3DC门。 响应于3DC门的传播和合并而产生第一和第二电路。 然后在不同的等价关系下对第二电路执行第一电路的组合等价检查。

公开(公告)号：US07240311B2

公开(公告)日：2007-07-03

申请号：US10995658

申请日：2004-11-22

Applicant: Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

Inventor： Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/504

Abstract: An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuit are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.

Abstract translation: 等价检查方法提供第一和第二逻辑功能。 不要在第一和第二逻辑功能中插入无门的条件。 无关门的插入产生第一中间电路和第二中间电路。 当3DC门和SDC门共存在第一和第二中间电路中时，第一中间电路的所有3DC门被传播并合并成单个3DC门。 当3DC门和SDC门共存在第一和第二中间电路中时，第二中间电路的所有3DC门都被传播并合并成单个3DC门。 响应于3DC门的传播和合并而产生第一和第二电路。 然后在不同的等价关系下对第二电路执行第一电路的组合等价检查。

公开(公告)号：US06842884B2

公开(公告)日：2005-01-11

申请号：US10230976

申请日：2002-08-28

Applicant: Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

Inventor： Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/504

Abstract: An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuits are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.

Abstract translation: 等价检查方法提供第一和第二逻辑功能。 不要在第一和第二逻辑功能中插入无门的条件。 无关门的插入产生第一中间电路和第二中间电路。 当3DC门和SDC门共存在第一和第二中间电路中时，第一中间电路的所有3DC门被传播并合并成单个3DC门。 当3DC门和SDC门共存在第一和第二中间电路中时，第二中间电路的所有3DC门都被传播并合并成单个3DC门。 响应于3DC门的传播和合并产生第一和第二电路。 然后在不同的等价关系下对第二电路执行第一电路的组合等价检查。