中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

147 records (took 0.025 seconds)

    NON-VOLATILE MEMORY DEVICES INCLUDING CHARGE STORAGE LAYERS
    2.
    发明申请
    NON-VOLATILE MEMORY DEVICES INCLUDING CHARGE STORAGE LAYERS 有权
    非易失性存储器件，包括充电储存层

    公开(公告)号：US20160240550A1

    公开(公告)日：2016-08-18

    申请号：US15043640

    申请日：2016-02-15

    Applicant: JAEHUN JUNG ,  ZHILIANG XIA ,  DAEWOONG KANG ,  DAE SIN KIM ,  KWANG SOO SEOL ,  HOMIN SON ,  SEUNGHYUN LIM

    Inventor： JAEHUN JUNG ,  ZHILIANG XIA ,  DAEWOONG KANG ,  DAE SIN KIM ,  KWANG SOO SEOL ,  HOMIN SON ,  SEUNGHYUN LIM

    IPC: H01L27/115 ,  H01L29/792 ,  H01L29/423

    CPC classification number: H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792 ,  H01L29/7923

    Abstract: A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.

    Abstract translation: 非易失性存储器件包括堆叠在衬底上的栅极电极，穿过栅极并连接到衬底的半导体图案，以及半导体图案和栅电极之间的电荷存储层。 电荷存储层包括半导体图形和栅电极之间的第一电荷存储层，第一电荷存储层和半导体图案之间的第二电荷存储层，以及第一电荷存储层和栅极之间的第三电荷存储层 电极。 第一电荷存储层的能带隙比第二和第三电荷存储层的能带隙小。 第一电荷存储层比第二和第三电荷存储层厚。

    Methods of manufacturing vertical semiconductor devices
    5.
    发明授权
    Methods of manufacturing vertical semiconductor devices 有权
    制造垂直半导体器件的方法

    公开(公告)号：US08697524B2

    公开(公告)日：2014-04-15

    申请号：US13212485

    申请日：2011-08-18

    Applicant: Byung-Kwan You ,  Kwang-Soo Seol ,  Young-Woo Park ,  Jin-Soo Lim

    Inventor： Byung-Kwan You ,  Kwang-Soo Seol ,  Young-Woo Park ,  Jin-Soo Lim

    IPC: H01L21/336

    CPC classification number: H01L21/28282 ,  H01L21/02104 ,  H01L27/11582 ,  H01L29/7926

    Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

    Abstract translation: 制造垂直半导体器件的方法可以包括形成包括牺牲层和绝缘夹层的模具结构，其中形成有第一开口。 牺牲层和绝缘夹层可以重复地和交替地层叠在基板上。 第一开口可能暴露基板。 可以通过氧化由第一开口暴露的牺牲层的部分来形成阻挡层。 分别可以在第一开口的侧壁上形成第一半导体层图案，电荷俘获层图案和隧道绝缘层图案。 可以在第一多晶硅层图案和第一开口的底部上形成第二半导体层。 可以部分去除牺牲层和绝缘夹层以形成第二开口。 可以去除牺牲层以在绝缘夹层之间形成凹槽。 控制栅电极可以形成在凹槽中。

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20140085961A1

    公开(公告)日：2014-03-27

    申请号：US14037547

    申请日：2013-09-26

    Applicant: Kohji KANAMORI ,  Youngwoo PARK ,  Jintaek PARK ,  Kwang Soo SEOL ,  Jaeduk LEE

    Inventor： Kohji KANAMORI ,  Youngwoo PARK ,  Jintaek PARK ,  Kwang Soo SEOL ,  Jaeduk LEE

    IPC: G11C5/06 ,  G11C13/00

    CPC classification number: G11C5/06 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/0023 ,  G11C2213/73 ,  H01L27/222 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

    Abstract: According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.

    Abstract translation: 根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制 全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。 多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和 第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

    Three-dimensional semiconductor memory device
    7.
    发明授权
    Three-dimensional semiconductor memory device 有权
    三维半导体存储器件

    公开(公告)号：US08530959B2

    公开(公告)日：2013-09-10

    申请号：US13198234

    申请日：2011-08-04

    Applicant: Sung-Il Chang ,  Youngwoo Park ,  Kwang Soo Seol

    Inventor： Sung-Il Chang ,  Youngwoo Park ,  Kwang Soo Seol

    IPC: H01L29/78

    CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    Abstract: Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.

    Abstract translation: 提供三维半导体器件。 一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层 的半导体图案以将半导体图案连接到基板。

    Nonvolatile Memory Devices Having Memory Cell Transistors Therein with Lower Bandgap Source/Drain Regions
    8.
    发明申请
    Nonvolatile Memory Devices Having Memory Cell Transistors Therein with Lower Bandgap Source/Drain Regions 有权
    具有存储单元晶体管的非易失性存储器件具有较低的带隙源/漏区

    公开(公告)号：US20110233610A1

    公开(公告)日：2011-09-29

    申请号：US12974542

    申请日：2010-12-21

    Applicant: Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

    Inventor： Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

    IPC: H01L29/772

    CPC classification number: H01L27/11521 ,  H01L27/11524

    Abstract: Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium.

    Abstract translation: 非易失性存储器件包括多个非易失性存储单元晶体管，其在由第一半导体材料形成的半导体层内的相应沟道区和由第二半导体材料形成的相应的源极/漏极区相互相对于第一半导体材料具有较小的带隙。 源极/漏极区域可以与沟道区域形成非整流结。 源极/漏极区域可以包括锗（例如Ge或SiGe区域），半导体层可以是P型硅层，并且多个非易失性存储单元晶体管的源极/漏极区域可以是P型锗或P 型硅锗。

    Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same
    10.
    发明申请
    Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same 审中-公开
    具有降低存储容量泄漏的易感性的非易失性存储器件及其形成方法

    公开(公告)号：US20110079839A1

    公开(公告)日：2011-04-07

    申请号：US12894863

    申请日：2010-09-30

    Applicant: Fayrushin Albert ,  Kwang Soo Seol ,  Jaeduk Lee

    Inventor： Fayrushin Albert ,  Kwang Soo Seol ,  Jaeduk Lee

    IPC: H01L29/788

    CPC classification number: H01L29/4234 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    Abstract: Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

    Abstract translation: 提供一种半导体器件。 半导体器件包括衬底，隧道绝缘层，电荷存储图案，阻挡层，栅电极。 隧道绝缘层设置在衬底上。 电荷存储图案设置在隧道绝缘层上。 电荷存储图案具有在上表面和侧壁之间的上表面，侧壁和边缘部分。 阻挡层包括覆盖电荷存储图案的边缘部分的绝缘图案，以及覆盖电荷存储图案的上表面，侧壁和边缘部分的栅极电介质层。 栅电极设置在阻挡层上，栅电极覆盖电荷存储图案的上表面，侧壁和边缘部分。

Patent Agency Ranking