公开(公告)号：US06366223B1

公开(公告)日：2002-04-02

申请号：US09350097

申请日：1999-07-09

申请人： Bhum Cheol Lee ,  Bong Soo Kim ,  Hee Bum Jung ,  Kwon Chul Park ,  Seok Youl Kang

发明人： Bhum Cheol Lee ,  Bong Soo Kim ,  Hee Bum Jung ,  Kwon Chul Park ,  Seok Youl Kang

IPC分类号： H03M700

CPC分类号： H03M5/04

摘要： A nibble inversion and block inversion code coding and decoding method and a coding and decoding apparatus for the same. The apparatus includes a disparity calculator for receiving a pre-code in which a nibble-inverted indication (NII) bit is added at the position next to the LSB of a source data of a n-bit (n represents an odd number higher than 3), computing a disparity Dpc value of the pre-code, computing a disparity value Dni of the odd bit nibble-inverted pre-code, decoding a code type in accordance with the value of the register and the value of the running digital sum RDS which represent the disparity code and outputting a control signal for manipulating the bits of the pre-code; a RDS calculator for outputting a RDS value which is obtained by accumulatively summing the disparity of the calculated code word by the unit of blocks for selecting a code word or a complement code word when the computed disparity Dpc is not 0; and a bit manipulator for selecting a nibble-inverted and block-inverted (NIBI) code type in accordance with a control signal from the disparity calculator, manipulating a bit of the inputted pre-code and generating a code word or a complement code word, for thereby providing a transition and a DC spectrum component of 0, using a 1-bit redundancy bit when a predetermined n-bit (n represents odd number) is coded, providing multiple frame patterns, and fully providing an in-band and out-band signal.

摘要翻译： 一种半字节反转和块反转码编码和解码方法及其编码和解码装置。 该装置包括：视差计算器，用于接收在n比特的源数据的LSB旁边的位置附加了半字节反转指示（NII）比特的预编码（n表示高于3的奇数） ），计算预编码的视差Dpc值，计算奇数比特半字节反相前置码的视差值Dni，根据寄存器的值解码码类型和运行数字和RDS的值 其代表差异码并输出用于操纵前置码的位的控制信号; RDS计算器，用于输出当所计算的视差Dpc不为0时通过用于选择代码字或补码的单元的单元累积求和所计算的代码字的视差获得的RDS值; 以及用于根据来自视差计算器的控制信号选择半字节反转和块反转（NIBI）码类型的位操纵器，操纵输入的预编码的位并产生码字或补码字， 从而提供转换和DC频谱分量为0，当预定的n位（n表示奇数）被编码时，使用1位冗余位，提供多个帧模式，并且完全提供带内和外部 频带信号。

公开(公告)号：US6104326A

公开(公告)日：2000-08-15

申请号：US136734

申请日：1998-08-19

申请人： Bhum Cheol Lee ,  Eun Chang Choi ,  Kwon Chul Park

发明人： Bhum Cheol Lee ,  Eun Chang Choi ,  Kwon Chul Park

IPC分类号： H03L7/00 ,  H03B27/00 ,  H03M5/06

CPC分类号： H03L7/0805 ,  H03L7/0995 ,  H04L7/0276 ,  H04L7/033

摘要： An apparatus for recovering high speed NRZ (non-return to zero) data is disclosed. A phase-locked loop (PLL) frequency-divides the frequency which is outputted from a voltage-controlled ring oscillator, and therefore, the physical limit of the PLL is not affected. The voltage-controlled ring oscillators are installed separately from the PLL, and the voltage-controlled ring oscillators are synchronized with the PLL in the frequency only. Further, the oscillators are phase-locked to the incoming NRZ data, and two voltage-controlled ring oscillators are enabled/disabled by the binary values of the NRZ data. Therefore, a bit synchronization is realized, and thus, the voltage-controlled ring oscillators are directly controlled by the NRZ data. Consequently, the NRZ data can be recovered up to the frequency band at which the voltage-controlled ring oscillators and a D flip flop operate.

摘要翻译： 公开了一种用于恢复高速NRZ（不归零）数据的装置。 锁相环（PLL）频率分频从压控环形振荡器输出的频率，因此PLL的物理极限不受影响。 压控环形振荡器与PLL分开安装，压控环形振荡器仅与频率同步。 此外，振荡器被锁相到进入的NRZ数据，并且两个压控环形振荡器由NRZ数据的二进制值启用/禁用。 因此，实现位同步，因此，电压控制的环形振荡器由NRZ数据直接控制。 因此，NRZ数据可以恢复到压控环形振荡器和D触发器工作的频带。

公开(公告)号：US5940018A

公开(公告)日：1999-08-17

申请号：US941214

申请日：1997-09-30

申请人： Jin-Young Kim ,  Bhum-Cheol Lee ,  Kwon-Chul Park

发明人： Jin-Young Kim ,  Bhum-Cheol Lee ,  Kwon-Chul Park

IPC分类号： H03M7/14 ,  H03M5/08 ,  H03M13/11 ,  H03M13/31 ,  H04B3/04 ,  H04L7/00 ,  H03M13/00

CPC分类号： H03M13/63 ,  H03M13/11 ,  H03M13/31 ,  H03M5/08

摘要： An nB2P coding/decoding device having a line code function facilitating data transmission and data recovery in the transmission line or link, and a function of a channel code for detecting errors in the recovered data, is provided, including: an nB2P coding device for dividing n bit width parallel data into two data units each having a predetermined bit width, and serial-transmitting the resulting n+2 bit coded data to which two odd parity bits are added, with predetermined n+2 bit with block synchronization data which is orthogonal to the coded data; and an nB2P decoding device for detecting the block synchronization data from the serially transmitted data, converts serial data to parallel form of n+2 bits, checking for errors in the coded data using the odd parity, and removing the odd parity to decode them into the original n bit width parallel data.

摘要翻译： 一种具有促进传输线或链路中的数据传输和数据恢复的线路代码功能的nB2P编码/解码装置，以及用于检测恢复数据中的错误的信道码的功能，包括：nB2P编码装置，用于分割 将n位宽的并行数据分割成具有预定位宽的两个数据单元，并且将具有两个奇校验位的所生成的n + 2位编码数据与预定的n + 2位串联发送，其中正交的块同步数据 到编码数据; 以及用于从串行发送数据检测块同步数据的nB2P解码装置，将串行数据转换成n + 2位的并行形式，使用奇校验检查编码数据中的错误，并且去除奇校验以将其解码为 原始n位宽的并行数据。

公开(公告)号：US5887040A

公开(公告)日：1999-03-23

申请号：US746992

申请日：1996-11-19

申请人： Hee-Young Jung ,  Bhum-Cheol Lee ,  Kwon-Chul Park

发明人： Hee-Young Jung ,  Bhum-Cheol Lee ,  Kwon-Chul Park

IPC分类号： H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L7/04

CPC分类号： H04L7/0338

摘要： The present invention provides a high speed digital data retiming apparatus, in which, in binary data bits transmitted at a high speed, the data can be retimed in a stable manner, even if there are present a static skew due to a delay difference between the retiming clock pulse and the data and a dynamic skew due to the characteristic variation according to time and temperature. Therefore, the present invention has the following advantages compared with the conventional apparatus. First, periodical and regular external clock pulses are delayed by means of a delaying section, so that system performance is independent of the pattern of data. Second, even if the data phases show a continuous difference (wandering) for more than a certain period of time, an elastic buffer absorbs the wandering, and therefore, no data loss is generated, with the result that the system is not put to a disorder condition. Third, even in the case where a metastable state occurs, its occurrence probability can be significantly reduced by utilizing logic, thereby making it possible to retime the data in stable manner.

摘要翻译： 本发明提供了一种高速数字数据重定时装置，其中，在以高速发送的二进制数据位中，即使存在静态偏移，也可以以稳定的方式重新定时， 重新定时钟脉冲和数据以及由于根据时间和温度的特性变化而产生的动态偏移。 因此，与现有技术相比，本发明具有以下优点。 首先，周期性和规则的外部时钟脉冲通过延迟部分被延迟，使得系统性能与数据模式无关。 第二，即使数据相位显示出持续的差异（漫游）一段时间，弹性缓冲器也可以吸收漂移，因此不会产生数据丢失，结果系统不会 无序状态。 第三，即使在发生亚稳态的情况下，也可以通过利用逻辑来显着降低其发生概率，从而使得可以以稳定的方式重新计算数据。

公开(公告)号：US6031886A

公开(公告)日：2000-02-29

申请号：US137747

申请日：1998-08-21

申请人： Ji Ha Nah ,  Hee Young Jung ,  Bhum Cheol Lee ,  Kwon Chul Park

发明人： Ji Ha Nah ,  Hee Young Jung ,  Bhum Cheol Lee ,  Kwon Chul Park

IPC分类号： H03L7/00 ,  H04L7/033 ,  H03D3/24

CPC分类号： H04L7/0338

摘要： The present invention provides a digital phase alignment which to select the clock whose the transition is occured in the close vicinity of a center of the input data unit interval, the rising transition or falling transition of data are detected, as a result, to generate the synthetic clock retiming data upon detecting the transition of data having a random bit column, the retiming clock is reached in the center of eye pattern of data, compared with a single directional transition is detected.

摘要翻译： 本发明提供一种数字相位对准，其选择在输入数据单位间隔的中心附近发生转变的时钟，检测数据的上升转变或下降转换，结果产生 在检测到具有随机位列的数据的转变时的合成时钟重新定时数据，与检测到单个方向转换相比，在眼图数据的中心达到重新定时时钟。

公开(公告)号：US5703882A

公开(公告)日：1997-12-30

申请号：US571077

申请日：1995-12-12

申请人： Hee Young Jung ,  Bhum Cheol Lee ,  Kwon Chul Park

发明人： Hee Young Jung ,  Bhum Cheol Lee ,  Kwon Chul Park

IPC分类号： G06F11/00 ,  G06F11/10 ,  H03M13/00 ,  H04L1/00 ,  H04L7/04 ,  H04L7/08 ,  H04L12/70 ,  H04L25/03 ,  H04Q11/04

CPC分类号： H04L1/0061 ,  G06F11/10 ,  H04L1/0041 ,  H04L25/03866 ,  H04L7/048 ,  H04Q11/0478 ,  H04L2012/5673

摘要： A modified cyclic line coding apparatus for error detection and frame recovery which generates a n-bit modified cyclic cord-word by use of k redundancy bits and partially scrambles the cyclic redundancy check bits using periodic scramble bits. The apparatus includes a transmitter including a modified cyclic redundancy generator unit for generating redundancy bits, a variable period sampled scrambler unit for partially scrambling the redundancy bits, a timing control unit for generating a timing signal, and a multiplexer unit for multiplexing input cell data in accordance with the timing signal. The apparatus also includes a receiver including a modified cyclic redundancy checker unit for outputting a block synchronization signal and sample bits when a block synchronization is detected, while outputting a synchronization error signal when no block synchronization is detected, a variable period sampled descrambler unit for generating descramble bits in accordance with the sample bits, a timing recovering unit for generating a timing signal, and a demultiplexer unit for demultiplexing the cell data in accordance with the timing signal. The apparatus can use various cell sizes, can stably receive the user information of cell data and can achieve an easy bit timing detection.

摘要翻译： 一种用于错误检测和帧恢复的修改的循环线编码装置，其通过使用k个冗余比特生成n位修改的循环线字，并且使用周期性扰频比特部分地对循环冗余校验位进行加扰。 该装置包括：发射机，包括用于产生冗余比特的修改的循环冗余发生器单元，用于对冗余比特进行部分加扰的可变周期采样扰频单元，用于产生定时信号的定时控制单元，以及用于复用输入单元数据的多路复用器单元 根据定时信号。 该装置还包括一个接收机，包括一个修改的循环冗余校验器单元，用于当检测到块同步时输出块同步信号和采样位，同时在没有检测到块同步时输出同步误差信号;可变周期采样解扰器单元，用于产生 根据采样位的解扰位，用于产生定时信号的定时恢复单元和用于根据定时信号对单元数据解复用的解复用器单元。 该装置可以使用各种小区大小，可以稳定地接收小区数据的用户信息，并且可以实现容易的比特定时检测。

公开(公告)号：US07681206B2

公开(公告)日：2010-03-16

申请号：US10941139

申请日：2004-09-14

申请人： Hyun Woo Oh ,  Moon Kyun Oh ,  Young Boo Kim ,  Kwon Chul Park

发明人： Hyun Woo Oh ,  Moon Kyun Oh ,  Young Boo Kim ,  Kwon Chul Park

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F15/16 ,  G06Q30/00

CPC分类号： H04L67/20 ,  H04L67/325 ,  H04L67/327 ,  Y10S715/961 ,  Y10S715/962

摘要： Provided are a system and a method for providing contents using an open API. A contents storing unit stores at least one contents. An open API unit is common to upper applications on the basis of a wired network interface and provides an API that is a communication function realized as components. A communication capability providing unit combines the API with the contents selected by the contents provider, and adds a communication function to the contents on the basis of usable network resources. The contents providing unit provides contents in which a communication function is added.

摘要翻译： 提供了一种使用开放API提供内容的系统和方法。 内容存储单元存储至少一个内容。 一个开放的API单元是基于有线网络接口的上层应用程序通用的，并提供作为组件实现的通信功能的API。 通信能力提供单元将API与内容提供者所选择的内容相结合，并根据可用的网络资源向内容添加通信功能。 内容提供单元提供添加通信功能的内容。

公开(公告)号：US06346895B1

公开(公告)日：2002-02-12

申请号：US09769099

申请日：2001-01-24

申请人： Bhum-Cheol Lee ,  Jong-Moo Sohn ,  Eun-Chang Choi ,  Kwon-Chul Park

发明人： Bhum-Cheol Lee ,  Jong-Moo Sohn ,  Eun-Chang Choi ,  Kwon-Chul Park

IPC分类号： H03M500

CPC分类号： H03M5/00

摘要： A method for using a nibble(partial bits of word) inversion code in a network system includes the steps of: a) adding 1 redundancy bit to n bit source data and generating a pre-code, n being an even number of 2 or over; b) deciding the number of transitions in the generated pre-code; c) determining the pre-code as a code word if the number of transitions in the pre-code is greater than or equal to 1+n/2 in a deciding result; d) inverting alternate bits including the redundancy bit among bits constructing the pre-code and generating the code word, if the number of transitions in the pre-code is less than n/2 in the deciding result; e) determining the pre-code as the code word in case that the number of transitions in the pre-code is equal to n/2 and simultaneously the source data is not an in-band signaling and not a special word in the deciding result; and f) inverting the nibble among the bits constructing the pre-code and generating the code word, in case that the number of transitions in the pre-code is equal to n/2 and simultaneously the source data is an in-band signaling or is a special word in the deciding result.

摘要翻译： 一种在网络系统中使用半字节（部分位字）反转码的方法包括以下步骤：a）将1个冗余比特加到n比特源数据并产生一个预编码，n是2或更多的偶数 ; b）决定生成的代码中的转换次数; c）如果所述预代码中的转换次数在决定结果中大于或等于1 + n / 2，则将所述预代码确定为代码字; d）如果所述预代码中的转换次数小于所述判定结果中的n / 2，则将包括构成所述预代码的位中的所述冗余位的交替位反转并生成所述代码字; e）在预编码中的转换次数等于n / 2并且同时源数据不是带内信令而不是决定结果中的特殊字的情况下，将前缀代码确定为码字 ; 以及f）在构成前代码的比特中产生半字节并产生码字，在预编码中的转换次数等于n / 2的情况下，并且源数据是带内信令或 是决定结果中的一个特殊字。

公开(公告)号：US5675293A

公开(公告)日：1997-10-07

申请号：US582882

申请日：1996-01-04

申请人： Bhum Cheol Lee ,  Jae Young Kim ,  Eun Chang Choi ,  Kwon Chul Park

发明人： Bhum Cheol Lee ,  Jae Young Kim ,  Eun Chang Choi ,  Kwon Chul Park

IPC分类号： H03K3/35 ,  H03K3/03 ,  H03B5/02

CPC分类号： H03K3/0315 ,  Y10S331/03

摘要： A voltage controlled ring oscillator having a reduced voltage controlled oscillator (VCO) gain by controlling only the fall time of the period of the VCO using integrated circuits and logic circuits. The VCO includes a mixer/inverter circuit, a logic circuit, a delay/inverter circuit, a first delay circuit, a second delay circuit, and a third delay circuit. The VCO gain is reduced by controlling only one pulse width of the logic level High and one pulse width of the logic level Low of the oscillating period. Furthermore, the VCO can be logically controlled by using a simple logic circuit as a component of the VCO.

摘要翻译： 通过仅使用集成电路和逻辑电路仅控制VCO的周期的下降时间，具有降压控制振荡器（VCO）增益的压控环形振荡器。 VCO包括混频器/反相器电路，逻辑电路，延迟/反相器电路，第一延迟电路，第二延迟电路和第三延迟电路。 通过仅控制逻辑电平高的一个脉冲宽度和振荡周期的逻辑电平低的一个脉冲宽度来减小VCO增益。 此外，可以通过使用简单的逻辑电路作为VCO的组件来逻辑地控制VCO。