公开(公告)号：US09276079B2

公开(公告)日：2016-03-01

申请号：US13617575

申请日：2012-09-14

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Keith Kwong Hon-Wong

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Keith Kwong Hon-Wong

IPC分类号： H01L21/31 ,  H01L29/51

CPC分类号： H01L29/518 ,  H01L27/24 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor.

公开(公告)号：US09059006B2

公开(公告)日：2015-06-16

申请号：US13523120

申请日：2012-06-14

申请人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Thekkemadathil V. Rajeevakumar ,  Keith Kwong Hon Wong

发明人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Thekkemadathil V. Rajeevakumar ,  Keith Kwong Hon Wong

IPC分类号： G01R27/08 ,  H01L23/52 ,  H01L29/10 ,  H01L27/06 ,  H01L23/525 ,  H01L27/112 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L27/0617 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

摘要翻译： 在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。 第一导电材料层和无定形金属氧化物沉积到凹陷区域中。 第二导电材料层填充凹部。 在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。 为了编程电反熔丝，电流在一对导电触点中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。 感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

公开(公告)号：US09016236B2

公开(公告)日：2015-04-28

申请号：US12185339

申请日：2008-08-04

申请人： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

发明人： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

IPC分类号： H01L21/306 ,  C23C16/00 ,  C23C16/507 ,  C23C16/34 ,  C23C16/40 ,  C23C16/455 ,  C23C16/458 ,  C23C16/56 ,  H01J37/20 ,  H01J37/32 ,  H01L27/108 ,  H01L21/316 ,  H01L21/318

CPC分类号： C23C16/507 ,  C23C16/345 ,  C23C16/402 ,  C23C16/45578 ,  C23C16/4586 ,  C23C16/56 ,  H01J37/20 ,  H01J37/321 ,  H01J2237/20207 ,  H01J2237/3323 ,  H01L21/31608 ,  H01L21/3185 ,  H01L27/10867

摘要： A high-density plasma chemical vapor deposition tool and the method for use of the tool is disclosed. The chemical vapor deposition tool allows for angular adjustment of the pedestal that holds the substrate being manufactured. Electromagnets serve as an “electron filter” that allows for angular deposition of material onto the substrate. Methods for fabrication of trench structures and asymmetrical spacers in a semiconductor manufacturing process are also disclosed. The angular deposition saves process steps, thereby reducing time, complexity, and cost of manufacture, while improving overall product yield.

摘要翻译： 公开了一种高密度等离子体化学气相沉积工具和该工具的使用方法。 化学气相沉积工具允许对保持正在制造的衬底的基座进行角度调节。 电磁铁用作允许将材料角度沉积到衬底上的“电子过滤器”。 还公开了在半导体制造工艺中制造沟槽结构和不对称间隔物的方法。 角度沉积节省了工艺步骤，从而降低了制造时间，复杂性和成本，同时提高了整体产品的产量。

公开(公告)号：US08895371B2

公开(公告)日：2014-11-25

申请号：US13605238

申请日：2012-09-06

申请人： Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

发明人： Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC分类号： H01L21/335 ,  H01L51/05 ,  H01L29/775 ,  H01L29/66 ,  H01L51/00 ,  H01L29/12 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/78

CPC分类号： H01L51/057 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/125 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7827 ,  H01L51/0045 ,  H01L51/0048 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

摘要： A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.

摘要翻译： 形成包括具有第一等电点的第一等电点材料层和具有小于第一等电点的第二等电点的第二等电子材料层的垂直交替堆叠的鳍结构。 第一和第二等电点材料层在具有第一和第二等电点之间的pH的溶液中相反地充电。 通过阴离子表面活性剂将负电荷赋予碳纳米管。 静电引力使得碳纳米管选择性地附着在第一等电点材料层的表面上。 碳纳米管沿翅片结构的水平长度方向自对准地附接到第一等电点材料层。 可以形成晶体管，其采用多个垂直排列的水平碳纳米管作为沟道。

公开(公告)号：US08815734B2

公开(公告)日：2014-08-26

申请号：US13290577

申请日：2011-11-07

申请人： Kangguo Cheng ,  Junli Wang ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Kangguo Cheng ,  Junli Wang ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76804 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76865 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A gas cluster ion beam process is used to reduce and/or even eliminate metal void formation in an interconnect structure. In one embodiment, gas cluster ion beam etching forms a chamfer opening in an interconnect dielectric material. In another embodiment, gas cluster ion beam etching reduces the overhang profile of a diffusion barrier or a multilayered stack of a diffusion barrier and a plating seed layer that is formed within an opening located in an interconnect dielectric material. In yet another embodiment, a gas cluster ion beam process deactivates a surface of an interconnect dielectric material that is located at upper corners of an opening that is formed therein. In this embodiment, the gas cluster ion beam process deposits a material that deactivates the upper corners of each opening that is formed into an interconnect dielectric material.

摘要翻译： 使用气体簇离子束工艺来减少和/或甚至消除互连结构中的金属空隙形成。 在一个实施例中，气体簇离子束蚀刻在互连电介质材料中形成倒角开口。 在另一个实施方案中，气体簇离子束蚀刻减少扩散阻挡层或扩散阻挡层的多层堆叠和形成在位于互连电介质材料中的开口内的电镀种子层的悬垂分布。 在另一个实施例中，气体团簇离子束过程使位于其中形成的开口的上角的互连电介质材料的表面失活。 在该实施例中，气体簇离子束处理沉积了使形成为互连电介质材料的每个开口的上角失活的材料。

公开(公告)号：US08796773B2

公开(公告)日：2014-08-05

申请号：US13539700

申请日：2012-07-02

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

IPC分类号： H01L27/12

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L21/823857

摘要： In a circuit structure, PFET devices have a gate dielectric including a high-k dielectric, a gatestack with a metal, a p-source/drain and silicide layer formed over the p-source/drain; NFET devices include a gate dielectric including a high-k dielectric, a gatestack with a metal, an n-source/drain and silicide layer formed over the n-source/drain. An epitaxial SiGe is present underneath and in direct contact with the PFET gate dielectric, while the epitaxial SiGe is absent underneath the NFET gate dielectric.

摘要翻译： 在电路结构中，PFET器件具有栅极电介质，其包括高k电介质，具有金属的栅格，p源极/漏极和形成在p源极/漏极上的硅化物层; NFET器件包括包括高k电介质的栅极电介质，具有金属的糖饼，在n源极/漏极上形成的n源极/漏极和硅化物层。 外延SiGe存在于PFET栅极电介质的下面并与PFET栅极电介质直接接触，而外延SiGe不存在于NFET栅极电介质下方。

公开(公告)号：US08767299B2

公开(公告)日：2014-07-01

申请号：US12906697

申请日：2010-10-18

申请人： Fei Liu ,  Qiqing C. Quyang ,  Keith Kwong Hon Wong

发明人： Fei Liu ,  Qiqing C. Quyang ,  Keith Kwong Hon Wong

IPC分类号： G02B5/18 ,  H01L21/30

CPC分类号： G02B5/18 ,  G02B5/1857 ,  G02B5/1866 ,  G02B6/124 ,  G02B2006/12107 ,  G03F7/2016 ,  H01L21/30

摘要： An embedded vertical optical grating, a semiconductor device including the embedded vertical optical grating and a method for forming the same. The method for forming the embedded optical grating within a substrate includes depositing a hard mask layer on the substrate, patterning at least one opening within the hard mask layer, vertically etching a plurality of scallops within the substrate corresponding to the at least one opening within the hard mask layer, removing the hard mask layer, and forming an oxide layer within the plurality of scallops to form the embedded vertical optical grating.

摘要翻译： 嵌入式垂直光栅，包括嵌入式垂直光栅的半导体器件及其形成方法。 用于在衬底内形成嵌入式光栅的方法包括在衬底上沉积硬掩模层，图案化硬掩模层内的至少一个开口，垂直蚀刻衬底内对应于在该掩模层内的至少一个开口的多个扇贝 硬掩模层，去除硬掩模层，以及在多个扇贝内形成氧化物层以形成嵌入的垂直光栅。

公开(公告)号：US08605499B2

公开(公告)日：2013-12-10

申请号：US13092247

申请日：2011-04-22

申请人： Leland Chang ,  Michael A. Guillorn ,  Dechao Guo ,  Fei Liu ,  Keith Kwong Hon Wong

发明人： Leland Chang ,  Michael A. Guillorn ,  Dechao Guo ,  Fei Liu ,  Keith Kwong Hon Wong

IPC分类号： G11C11/50

CPC分类号： H03H9/2457 ,  G11C11/404 ,  G11C23/00 ,  H03H2009/02314

摘要： Systems and methods for operating a nanometer-scale cantilever beam with a gate electrode. An example system includes a drive circuit coupled to the gate electrode where a drive signal from the circuit may cause the beam to oscillate at or near the beam's resonance frequency. The drive signal includes an AC component, and may include a DC component as well. An alternative example system includes a nanometer-scale cantilever beam, where the beam oscillates to contact a plurality of drain regions.

摘要翻译： 用栅电极操作纳米级悬臂梁的系统和方法。 示例性系统包括耦合到栅电极的驱动电路，其中来自电路的驱动信号可以使光束在光束的共振频率处或其附近振荡。 驱动信号包括AC分量，并且还可以包括DC分量。 替代示例系统包括纳米级悬臂梁，其中光束振荡以接触多个漏极区域。

公开(公告)号：US08466443B2

公开(公告)日：2013-06-18

申请号：US12827197

申请日：2010-06-30

申请人： Terence L. Kane ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

发明人： Terence L. Kane ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

IPC分类号： H01L29/02

CPC分类号： H01L45/1616 ,  G11C17/14 ,  H01C7/1013 ,  H01C7/105 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a voltage sensitive resistor (VSR) write once (WO) read only memory (ROM) device which includes a semiconductor device and a VSR connected to the semiconductor device. The VSR WO ROM device is a write once read only device. The VSR includes a CVD titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by an order of 102, more preferably 103 and most preferably 104 when a predetermined voltage and current are applied to the VSR. A plurality of the VSR WO ROM devices may be arranged to form a high density programmable logic circuit in a 3-D stack. Also disclosed are methods to form the VSR WO ROM device.

摘要翻译： 公开了一种包括半导体器件和连接到半导体器件的VSR的一次（WO）只读存储器（ROM）器件的电压敏感电阻器（VSR）。 VSR WO ROM设备是一次写入只读设备。 VSR包括具有残留钛 - 碳键合的CVD氮化钛层，使得VSR是形成的电阻的，并且当预定的电压和电流被施加到电阻时，可以变得更小的电阻性为102，更优选为103，最优选为104。 VSR。 多个VSR WO ROM器件可以被布置成在3-D堆栈中形成高密度可编程逻辑电路。 还公开了形成VSR WO ROM器件的方法。

公开(公告)号：US08421228B2

公开(公告)日：2013-04-16

申请号：US13405443

申请日：2012-02-27

申请人： Ying Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Ying Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76844 ,  H01L21/76846 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact structure and a method of forming the contact structure. The structure includes: a silicide layer on and in direct physical contact with a top substrate surface of a substrate; an electrically insulating layer on the substrate; and an aluminum plug within the insulating layer. The aluminum plug has a thickness not exceeding 25 nanometers in a direction perpendicular to the top substrate surface. The aluminum plug extends from a top surface of the silicide layer to a top surface of the insulating layer. The aluminum plug is in direct physical contact with the top surface of the silicide layer and is in direct physical contact with the silicide layer. The method includes: forming the silicide layer on and in direct physical contact with the top substrate surface of the substrate; forming the electrically insulating layer on the substrate; and forming the aluminum plug within the insulating layer.

摘要翻译： 接触结构和形成接触结构的方法。 该结构包括：与衬底的顶部衬底表面直接物理接触的硅化物层; 基板上的电绝缘层; 和绝缘层内的铝塞。 该铝塞的垂直于顶部基板表面的方向的厚度不超过25纳米。 铝塞从硅化物层的顶表面延伸到绝缘层的顶表面。 铝插塞与硅化物层的顶表面直接物理接触并与硅化物层直接物理接触。 该方法包括：在衬底的顶部衬底表面上直接物理接触形成硅化物层; 在基板上形成电绝缘层; 以及在所述绝缘层内形成所述铝塞。