公开(公告)号：US09261940B2

公开(公告)日：2016-02-16

申请号：US13396618

申请日：2012-02-15

申请人： Bo-geun Kim ,  Kye-hyun Kyung ,  Jae-yong Jeong ,  Seung-hun Choi ,  Seok-cheon Kwon ,  Chul-ho Lee

发明人： Bo-geun Kim ,  Kye-hyun Kyung ,  Jae-yong Jeong ,  Seung-hun Choi ,  Seok-cheon Kwon ,  Chul-ho Lee

IPC分类号： G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00 ,  G06F1/32 ,  G06F1/14 ,  G06F13/16 ,  G06F1/04 ,  G11C7/22

CPC分类号： G06F1/12 ,  G06F1/04 ,  G06F1/14 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0683 ,  G06F13/1689 ,  G11C7/222 ,  Y02D10/14

摘要： A memory system includes a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

摘要翻译： 存储器系统包括产生处理器时钟的控制器和多个存储器件，每个存储器件包括与处理器时钟同步地产生内部时钟的内部时钟发生器，以及与该处理器时钟同步地执行峰值电流产生操作的存储器 内部时钟，其中至少两个存储器件在不同时间产生它们各自的内部时钟，使得相应的峰值电流产生操作在不同的时间执行。

公开(公告)号：USRE44064E1

公开(公告)日：2013-03-12

申请号：US13173495

申请日：2011-06-30

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： G11C8/00

摘要： The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.

摘要翻译： 本发明涉及具有双倍数据速率的同步半导体存储器件，更具体地说，涉及一种使用自由运行时钟输入和输出数据的同步半导体存储器件，并将表示数据开始的前导码输入到输出数据中。 本发明的半导体存储器件响应于从外部输入的预定时钟信号从存储器件的外部接收数据读取命令，并且响应于时钟信号输出包括前置码的数据。

公开(公告)号：US08120976B2

公开(公告)日：2012-02-21

申请号：US11826311

申请日：2007-07-13

申请人： Eunsung Seo ,  Kye-hyun Kyung

发明人： Eunsung Seo ,  Kye-hyun Kyung

IPC分类号： G11C29/00

CPC分类号： G11C29/02 ,  G11C29/025

摘要： Example embodiments relate to a line defect detection circuit, including a first driver disposed at one end of a line and configured to drive the line using a first voltage or a second voltage in response to a control signal, and a second driver disposed at the other end of the line and configured to drive the line using the second voltage in response to a stress signal.

摘要翻译： 线路缺陷检测电路的示例性实施例涉及一种线缺陷检测电路，该电路缺陷检测电路包括设置在一端的第一驱动器，并被配置为响应于控制信号而使用第一电压或第二电压来驱动线路;以及第二驱动器，设置在另一端 并且被配置为响应于应力信号使用第二电压来驱动线路。

公开(公告)号：US07679975B2

公开(公告)日：2010-03-16

申请号：US11806577

申请日：2007-06-01

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： G11C29/00

CPC分类号： G11C29/808

摘要： A semiconductor memory device includes a plurality of memory areas. Each of the memory areas includes a normal cell array and a redundancy cell array for repairing defective cells generated in the normal cell array such that the semiconductor memory device is usable even when memory arrays include defective cells. A size of a redundancy cell array of a first memory area is greater than a size of the redundancy cell arrays of the other memory areas.

公开(公告)号：US07369445B2

公开(公告)日：2008-05-06

申请号：US11315470

申请日：2005-12-22

申请人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

发明人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

IPC分类号： G11C7/10

CPC分类号： G06F13/1694 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/4093

摘要： A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.

摘要翻译： 可以提供一种操作包括耦合到命令地址总线的多个存储器件的存储器系统的方法。 特别地，多个存储器件的第一存储器件可以被设置为第一操作模式，并且多个存储器件中的第二存储器件可以被设置为与第一操作模式不同的第二操作模式。 此外，可以响应于通过命令地址总线提供给多个存储器件的读/写命令地址信号执行读/写操作，使得第一存储器件在读/写期间根据第一操作模式进行操作 并且使得第二存储器件在读/写操作期间根据第二操作模式操作。 还讨论了相关系统。

公开(公告)号：US20050162964A1

公开(公告)日：2005-07-28

申请号：US11015391

申请日：2004-12-16

申请人： Kye-Hyun Kyung ,  Kyu-Han Han

发明人： Kye-Hyun Kyung ,  Kyu-Han Han

IPC分类号： G11C5/00 ,  G11C7/00 ,  G11C8/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/408

CPC分类号： G11C11/4087 ,  G11C8/08 ,  G11C8/18 ,  G11C11/406 ,  G11C2211/4067

摘要： A dynamic semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs. A mode setting portion receives a mode setting code applied from an external portion to generate a power saving mode control signal for a power saving mode of operation responsive to a mode setting command. An address control portion decodes an address applied from an external portion or a refresh address to select one of the plurality of the word lines during a normal mode operation. The address control portion also selects a predetermined number of bits of the address during a power saving mode of operation. The semiconductor memory device, therefore extends the refresh cycle while reducing the refresh time resulting in a lower power consumption.

摘要翻译： 动态半导体存储器件包括存储单元阵列，其包括连接在多个字线和多个位线对之间的多个存储单元。 模式设置部分接收从外部部分施加的模式设置代码，以响应于模式设置命令产生用于功率节省模式的功率节省模式控制信号。 在正常模式操作期间，地址控制部分对从外部施加的地址或刷新地址进行解码以选择多个字线中的一个。 地址控制部分还在省电操作模式期间选择地址的预定数量的位。 因此，半导体存储器件延长刷新周期，同时减少刷新时间，导致更低的功耗。

公开(公告)号：US20050041491A1

公开(公告)日：2005-02-24

申请号：US10834490

申请日：2004-04-29

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： G11C29/04 ,  G11C7/00 ,  G11C29/00

CPC分类号： G11C29/785 ,  G11C29/4401 ,  G11C29/808 ,  G11C2029/1208 ,  G11C2029/4402

摘要： Provided are a repair apparatus and method in a semiconductor memory device, the repair apparatus being selectively programmed suitable for a wafer-level test or a post package test. The repair apparatus includes a repair control circuit, a redundancy memory cell array, and a redundancy decoder. The repair control circuit programs one of an address signal for a first defective cell of the main memory cell array and an address signal for a second defective cell of the main memory cell array and outputs a control signal in response to the address signal undergoing the first decoding operation, the first defective cell being detected during a wafer-level test and the second defective cell being detected during a post package test. The redundancy memory cell array includes a plurality of redundancy memory cells and is activated to repair one of the first and second defective cells. The redundancy decoder is enabled or disabled in response to the control signal and is enabled to activate parts of the redundancy memory cells. The normal decoder is disabled in response to the control signal when the redundancy decoder is enabled.

摘要翻译： 提供了半导体存储器件中的修复装置和方法，修复装置被选择性地编程适用于晶片级测试或后封装测试。 修理装置包括修理控制电路，冗余存储单元阵列和冗余解码器。 修复控制电路对主存储单元阵列的第一有缺陷单元的地址信号和主存储单元阵列的第二缺陷单元的地址信号进行编程，并响应于经历第一 解码操作，在晶片级测试期间检测到第一有缺陷单元，并且在后封装测试期间检测第二有缺陷单元。 冗余存储单元阵列包括多个冗余存储单元，并被激活以修复第一和第二有缺陷单元之一。 冗余解码器响应于控制信号而被使能或禁止，并且能够激活冗余存储单元的部分。 当冗余解码器被使能时，响应于控制信号禁用正常解码器。

公开(公告)号：US20050001305A1

公开(公告)日：2005-01-06

申请号：US10884407

申请日：2004-07-02

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： H01L25/18 ,  H01L23/12 ,  H01L25/065 ,  H01L25/07 ,  H01L23/52 ,  H01L23/02 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L2224/32014 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/4911 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01068 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00014

摘要： Provided is a stack type semiconductor package. The semiconductor package includes a first substrate, a first semiconductor chip, a second substrate, at least one second semiconductor chip and at least one third substrate. The first substrate has external connection terminals mounted on a first surface and a plurality of lands on a second surface that is an opposite side of the first surface. The first semiconductor chip is mounted on the second surface of the first substrate. The second substrate is attached at its first surface to the first semiconductor chip and includes plural outer lands in an outer perimeter of the second surface that is the opposite side of the first surface, a window penetrating between the first and second surface, inner lands around the window of the second surface. The second semiconductor chip is mounted on the second surface of the second substrate. At least one third substrate is attached to the first surface of the second semiconductor chip and includes plural inner lands in the outer perimeter of the second surface that is the opposite side of the first surface, and the window penetrating between the first and second surface, and the inner lands around the window of the second surface. The first and second semiconductor chips have a center pad structure.

摘要翻译： 提供了一种堆叠型半导体封装。 半导体封装包括第一衬底，第一半导体芯片，第二衬底，至少一个第二半导体芯片和至少一个第三衬底。 第一基板具有安装在第一表面上的外部连接端子和与第一表面相对的第二表面上的多个焊盘。 第一半导体芯片安装在第一基板的第二表面上。 第二基板在其第一表面附接到第一半导体芯片，并且包括位于第二表面的与第一表面相反的一侧的外周边中的多个外部凸台，在第一和第二表面之间穿透的窗口， 第二个表面的窗口。 第二半导体芯片安装在第二基板的第二表面上。 至少一个第三衬底附接到第二半导体芯片的第一表面，并且包括位于第二表面的与第一表面相反的一侧的外周中的多个内部平台，并且窗口在第一和第二表面之间穿透， 以及第二表面的窗口周围的内部区域。 第一和第二半导体芯片具有中心焊盘结构。

公开(公告)号：US06667916B2

公开(公告)日：2003-12-23

申请号：US10073525

申请日：2002-02-11

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： G11C2900

CPC分类号： G11C29/46

摘要： A semiconductor memory device having a mode control circuit includes a mode entrance portion for outputting an output signal in response to an external control signal, a mode entrance control portion for generating a mode entrance enable signal, MDEN, for controlling entry by the semiconductor device into a specific mode, for example a test mode, and a logic portion for combining the two to generate a mode signal for setting the specific mode. The mode entrance control portion includes a first and second fusing portion each including a fuse and a power-up signal for activating the MDEN in a case where the first and second fuses are maintained at an initial state or are changed at the initial state, and deactivating the MDEN otherwise. The mode control circuit prevents improper entry into the specific mode.

摘要翻译： 具有模式控制电路的半导体存储器件包括用于响应于外部控制信号输出输出信号的模式入口部分，用于产生模态入口使能信号的模态入口控制部分MDEN，用于控制半导体器件进入 特定模式，例如测试模式，以及用于组合两者以产生用于设置特定模式的模式信号的逻辑部分。 模式入口控制部分包括第一和第二定影部分，每个第一和第二熔断部分包括熔丝和用于在第一和第二熔丝保持初始状态或在初始状态下改变的情况下激活MDEN的上电信号;以及 否则禁用MDEN。 模式控制电路防止不正确地进入特定模式。

公开(公告)号：US06525417B2

公开(公告)日：2003-02-25

申请号：US10124211

申请日：2002-04-16

申请人： Bong-seok Chae ,  Kye-hyun Kyung

发明人： Bong-seok Chae ,  Kye-hyun Kyung

IPC分类号： H01L2348

CPC分类号： H01L23/5222 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： A step height between first and second elevated conductive lines that are laterally spaced apart on an integrated circuit substrate may be reduced by forming a dummy conductive line beneath the second conductive line, to further elevate the second conductive line on the integrated circuit substrate. Depth-of-focus may thereby be improved so that reliability of the conductive lines may also be improved. The second conductive line and the dummy conductive line vertically overlap by an amount that is less than one half the width of the second conductive line. Thus, the capacitance between the second conductive line and the dummy conductive line may be reduced. Undue delay therefore need not be created by introduction of the dummy conductive line.

摘要翻译： 可以通过在第二导线下方形成虚拟导电线来进一步提高集成电路基板上的第二导线，从而减小在集成电路基板上横向隔开的第一和第二升高的导线之间的台阶高度。 因此可以提高聚焦深度，从而也可以提高导电线的可靠性。 第二导线和虚拟导电线垂直重叠的量小于第二导线宽度的一半。 因此，可以减小第二导线与虚拟导电线之间的电容。 因此不需要通过引入虚拟导线来产生不适当的延迟。