利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

104 条记录 (耗时 0.024 秒)

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
    半导体器件及制造半导体器件的方法

    公开(公告)号：US20170062327A1

    公开(公告)日：2017-03-02

    申请号：US15191558

    申请日：2016-06-24

    申请人： Kyoung-hoon KIM ,  Woo-sung YANG ,  Jee-hoon HWANG

    发明人： Kyoung-hoon KIM ,  Woo-sung YANG ,  Jee-hoon HWANG

    IPC分类号： H01L23/528 ,  H01L21/321 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768

    CPC分类号： H01L23/528 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76892 ,  H01L27/11517 ,  H01L27/11563 ,  H01L27/11582 ,  H01L28/00

    摘要： A semiconductor device includes a plurality of line patterns formed apart from one another on a substrate, the plurality of line patterns having a first width and extending parallel to one another in a first direction. A first line pattern of the plurality of line patterns may include a wider portion having a second width in a second direction perpendicular to the first direction that is greater than the first width. One or more second line patterns may be located adjacent to the first line pattern and include a conformal portion conformally formed about the wider portion of the first line pattern. One or more third line patterns may be located adjacent to the second line pattern and include an end portion near the conformal portion of the one or more second line pattern.

    摘要翻译： 半导体器件包括在衬底上彼此分开形成的多个线图案，多个线图案具有第一宽度并且在第一方向上彼此平行延伸。 多个线图案的第一线图案可以包括在垂直于大于第一宽度的第一方向的第二方向上具有第二宽度的较宽部分。 可以将一个或多个第二线图案定位成与第一线图案相邻，并且包括围绕第一线图案的较宽部分共形地形成的共形部分。 一个或多个第三线图案可以位于与第二线图案相邻并且包括在一个或多个第二线图案的保形部分附近的端部。

    VERTICAL NAND FLASH MEMORY DEVICE
    2.
    发明申请
    VERTICAL NAND FLASH MEMORY DEVICE 有权
    垂直NAND闪存存储器件

    公开(公告)号：US20160343727A1

    公开(公告)日：2016-11-24

    申请号：US14992154

    申请日：2016-01-11

    申请人： Kyoung-Hoon KIM ,  Hongsoo KIM

    发明人： Kyoung-Hoon KIM ,  Hongsoo KIM

    IPC分类号： H01L27/115 ,  H01L23/528

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： Provided is a vertical NAND flash memory device. The vertical NAND flash memory device may include word lines formed on a substrate, a plurality of pads horizontally extending from the word lines, and contact plugs connected to respective pads. The contact plugs may include a first contact plug connected to a lowermost pad that is closest to the substrate, and a set of second contact plugs each second contact plug connected to a corresponding pad of the plurality of pads. A first distance between the first contact plug and a second contact plug of the set of second contact plugs that is adjacent to the first contact plug may be different from second distances between adjacent contact plugs of the set of second contact plugs. The second distances may be substantially the same as each other.

    摘要翻译： 提供了一种垂直NAND闪存设备。 垂直NAND闪存器件可以包括形成在基板上的字线，从字线水平延伸的多个焊盘以及连接到相应焊盘的接触插头。 接触插塞可以包括连接到最靠近衬底的最下垫的第一接触插塞和一组第二接触插塞，每个第二接触插塞连接到多个衬垫的相应衬垫。 所述第一接触插塞和与所述第一接触插塞相邻的所述一组第二接触插塞的第二接触插塞之间的第一距离可以不同于所述一组第二接触插塞的相邻接触插塞之间的第二距离。 第二距离可以彼此基本相同。

    Light emitting device having vertically stacked light emitting diodes
    4.
    发明授权
    Light emitting device having vertically stacked light emitting diodes 有权
    具有垂直堆叠的发光二极管的发光器件

    公开(公告)号：US08598598B2

    公开(公告)日：2013-12-03

    申请号：US12775008

    申请日：2010-05-06

    申请人： Sung Han Kim ,  Kyoung Hoon Kim

    发明人： Sung Han Kim ,  Kyoung Hoon Kim

    IPC分类号： H01L27/15

    CPC分类号： H01L33/08 ,  H01L27/153

    摘要： Disclosed is a light emitting device having vertically stacked light emitting diodes. It comprises a lower semiconductor layer of a first conductive type positioned on a substrate, a semiconductor layer of a second conductive type on the lower semiconductor layer of a first conductive type, and an upper semiconductor layer of a first conductive type on the semiconductor layer of a second conductive type. Furthermore, a lower active layer is interposed between the lower semiconductor layer of a first conductive type and the semiconductor layer of a second conductive type, and an upper active layer is interposed between the semiconductor layer of a second conductive type and the upper semiconductor layer of a first conductive type. Accordingly, there is provided a light emitting device having a structure in which a lower light emitting diode comprising the lower active layer and an upper light emitting diode comprising the upper active layer are vertically stacked. Therefore, light output per unit area of the light emitting device is enhanced as compared with a conventional light emitting device, and thus, a chip area of the light emitting device needed to obtain the same light output as the conventional light emitting device can be reduced.

    摘要翻译： 公开了一种具有垂直堆叠的发光二极管的发光器件。 它包括位于基板上的第一导电类型的下半导体层，在第一导电类型的下半导体层上的第二导电类型的半导体层和第一导电类型的半导体层上半导体层 第二导电类型。 此外，在第一导电类型的下半导体层和第二导电类型的半导体层之间插入下有源层，并且上有源层插入在第二导电类型的半导体层和第二导电类型的半导体层之间 第一导电类型。 因此，提供了一种发光器件，其具有如下结构，其中包括下部有源层的下部发光二极管和包括上部有源层的上部发光二极管垂直堆叠。 因此，与传统的发光器件相比，发光器件的每单位面积的光输出增强，因此可以减少获得与常规发光器件相同的光输出所需的发光器件的芯片面积 。

    Nonvolatile memory devices having a three dimensional structure
    7.
    发明授权
    Nonvolatile memory devices having a three dimensional structure 有权
    具有三维结构的非易失性存储器件

    公开(公告)号：US08203211B2

    公开(公告)日：2012-06-19

    申请号：US12798525

    申请日：2010-04-06

    申请人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

    发明人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

    IPC分类号： H01L27/115 ,  H01L23/522

    CPC分类号： H01L27/11578 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11582

    摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

    摘要翻译： 具有三维结构的非易失性存储装置。 非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。