公开(公告)号：US08456397B2

公开(公告)日：2013-06-04

申请号：US12476716

申请日：2009-06-02

申请人： Sung-soo Kim ,  Kyu-chan Lee ,  Hyeong-sik Choi

发明人： Sung-soo Kim ,  Kyu-chan Lee ,  Hyeong-sik Choi

IPC分类号： G09G3/36 ,  G09G5/10

CPC分类号： G09G3/3648 ,  G09G2310/06 ,  G09G2320/0252 ,  G09G2320/0257 ,  G09G2340/16 ,  G09G2360/18

摘要： A display apparatus for calibrating a grayscale data including a timing controller, and a method for driving a panel are provided. A display apparatus includes a timing controller which calibrates the grayscale data of the current frame using the grayscale data of the previous and the current frame and a driving unit which drives a panel using the calibrated grayscale data of the current frame. By generating calibrated grayscale data which are variable according to the change of grayscale, response times of liquid crystal may be improved.

摘要翻译： 提供了用于校准包括定时控制器的灰度数据的显示装置和用于驱动面板的方法。 显示装置包括使用前一帧和当前帧的灰阶数据来校准当前帧的灰阶数据的定时控制器，以及使用当前帧的校准灰度数据来驱动面板的驱动单元。 通过生成根据灰度变化可变的校准灰度数据，可以提高液晶的响应时间。

公开(公告)号：US20070263461A1

公开(公告)日：2007-11-15

申请号：US11826367

申请日：2007-07-13

申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Young-Hun Seo

IPC分类号： G11C7/00

CPC分类号： G11C11/4078 ,  G11C7/24

摘要： A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on.

公开(公告)号：US06678206B2

公开(公告)日：2004-01-13

申请号：US10106931

申请日：2002-03-25

申请人： Yong-Gyu Chu ,  Kyu-Chan Lee

发明人： Yong-Gyu Chu ,  Kyu-Chan Lee

IPC分类号： G11C800

CPC分类号： G11C8/18 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2227 ,  H03L7/0812 ,  H03L7/089 ,  H03L7/0891

摘要： A semiconductor memory device including a delay locked loop (DLL) that is capable of turning off the DLL in a precharge mode while maintaining locking information stored before the DLL operates in the precharge mode is provided. The DLL includes an ON/OFF mode for turning the DLL on or off. The DLL also includes a standby mode for turning the DLL off while still maintaining locking information stored before the DLL operates in a precharge mode in response to the activation of a standby enabling signal. The standby enabling signal is inactive when the DLL locks. The standby enabling signal is active when DLL lock is complete.

摘要翻译： 提供一种包括延迟锁定环（DLL）的半导体存储器件，其能够在保持DLL在预充电模式之前存储的锁定信息的同时以预充电模式关闭DLL。 该DLL包括用于打开或关闭DLL的ON / OFF模式。 DLL还包括用于响应于待机使能信号的激活而在DLL在预充电模式之前存储的锁定信息的同时仍然保持关闭DLL的待机模式。 当DLL锁定时，待机启用信号无效。 当DLL锁定完成时，待机启用信号有效。

公开(公告)号：US06175263B1

公开(公告)日：2001-01-16

申请号：US09104857

申请日：1998-06-24

申请人： Kyu-chan Lee ,  Hong-il Yoon

发明人： Kyu-chan Lee ,  Hong-il Yoon

IPC分类号： G05F110

CPC分类号： G05F3/205

摘要： A back bias generator for a semiconductor device improves refresh characteristics, reduces leakage current, and increases back bias supply capacity in a DRAM having a triple well structure by applying a well bias voltage to the bulk of an NMOS transfer transistor. The back bias generator includes a well bias generator that generates the well bias voltage before the pumping voltage is applied to the transfer transistor. The well bias provides a back bias to a parasitic NPN transistor formed in the triple well of the NMOS transfer transistor, thereby preventing leakage through the NPN into the substrate. The well bias is also applied to the bulk of a clamp transistor that initializes a pumping capacitor.

摘要翻译： 用于半导体器件的背偏置发生器通过向NMOS传输晶体管的本体施加阱偏置电压来改善具有三阱结构的DRAM中的刷新特性，减小漏电流并增加背偏置电源容量。 背偏置发生器包括井偏压发生器，其在将泵浦电压施加到转移晶体管之前产生阱偏置电压。 阱偏压为在NMOS传输晶体管的三阱中形成的寄生NPN晶体管提供反偏压，从而防止NPN中漏入衬底。 阱偏压也适用于初始化泵浦电容器的钳位晶体管的大部分。

公开(公告)号：US5701268A

公开(公告)日：1997-12-23

申请号：US701892

申请日：1996-08-23

申请人： Kyu-chan Lee ,  Sang-bo Lee ,  Jai-hoon Sim

发明人： Kyu-chan Lee ,  Sang-bo Lee ,  Jai-hoon Sim

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/407 ,  G11C11/4091

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： Integrated circuit memory devices include at least first and second memory cells electrically coupled to respective first and second sense bit signal lines of a sense amplifier. The sense amplifier comprises a circuit for amplifying a difference in potential between the first and second sense bit signal lines by driving these lines to respective first and second different potentials. A driving circuit is also provided for simultaneously driving the first and second sense bit signal lines towards the first potential in response to application of a boost control signal. This driving circuit preferably comprises a first capacitor electrically connected in series between the boost control input and the first sense bit signal line and a second capacitor electrically connected in series between the boost control input and the second sense bit signal line. The boost control signal is established at the first potential to drive both the sense bit signal lines from different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) towards the first potential, prior to amplification of the difference in potential between the first and second sense bit signal lines by the sense amplifier. The present invention enables the sense amplifier to operate in an environment where the power supply voltage (e.g., VCC) is reduced and the different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) to be amplified are initially established at potentials below the normal sensitivity of the sense amplifier.

摘要翻译： 集成电路存储器件包括电耦合到读出放大器的相应第一和第二感测位信号线的至少第一和第二存储器单元。 感测放大器包括用于通过将这些线驱动到相应的第一和第二不同电位来放大第一和第二感测位信号线之间的电位差的电路。 还提供驱动电路，用于响应于施加升压控制信号，同时将第一和第二感测位信号线驱动朝向第一电位。 该驱动电路优选地包括串联电连接在升压控制输入和第一感测位信号线之间的第一电容器和串联电连接在升压控制输入和第二感测位信号线之间的第二电容器。 升压控制信号被建立在第一电位，以驱动来自不同中间电位（例如，+ E，fra 1/2 + EE VCC +，+ E，fra 1/2 + EE VCC）的感测位信号线朝着第一 在由感测放大器放大第一和第二感测位信号线之间的电位差之前的电位。 本发明使得读出放大器能够在电源电压（例如，VCC）减小的环境中工作，并且不同的中间电位（例如，+ E，fra 1/2 + EE VCC +，+ E， + EE VCC）最初建立在低于读出放大器正常灵敏度的电位。

公开(公告)号：US5657282A

公开(公告)日：1997-08-12

申请号：US400995

申请日：1995-03-09

申请人： Kyu-Chan Lee

发明人： Kyu-Chan Lee

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/50 ,  G11C11/401

摘要： A semiconductor integrated circuit with a stress circuit and a stress voltage supplying method thereof ensures the reliability of the device. The semiconductor integrated circuit has a stress enable circuit for generating an enable signal during a test operation of the chip and for enabling the test operation, a stress voltage supplying circuit for supplying a first stress voltage and a second stress voltage in response to an output signal of the stress enable circuit during the test operation, and a sensing delay control circuit for receiving the first and second stress voltages and for delaying an operation of the sense amp control circuit during the test operation. During the test operation, the first and second stress voltages are supplied to word lines adjacent to each other in response to the output signal of the stress enable circuit, and a state of a selected memory cell by the word line is sensed in response to an output signal of the sensing delay control circuit.

摘要翻译： 具有应力电路和应力电压提供方法的半导体集成电路确保了器件的可靠性。 半导体集成电路具有应力使能电路，用于在芯片的测试操作期间产生使能信号并使能测试操作;应力电压供应电路，用于响应输出信号提供第一应力电压和第二应力电压 以及用于接收第一和第二应力电压并用于在测试操作期间延迟读出放大器控制电路的操作的感测延迟控制电路。 在测试操作期间，第一和第二应力电压响应于应力使能电路的输出信号被提供给彼此相邻的字线，并且响应于一个字线检测所选择的存储单元的状态 感测延迟控制电路的输出信号。

公开(公告)号：US20130329489A1

公开(公告)日：2013-12-12

申请号：US13832101

申请日：2013-03-15

申请人： HYE-JIN KIM ,  Sang-Kyu Kang ,  Dong-Hyun Sohn ,  Dong-Min Kim ,  Kyu-Chan Lee

发明人： HYE-JIN KIM ,  Sang-Kyu Kang ,  Dong-Hyun Sohn ,  Dong-Min Kim ,  Kyu-Chan Lee

IPC分类号： G11C11/16

CPC分类号： G11C11/1675 ,  G11C5/147 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

摘要： A MRAM includes a memory cell array of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells. A source line voltage generator generates a source line driving voltage in response to an external power supply voltage and provides the source line driving voltage to the source line.

摘要翻译： MRAM包括自旋转移转矩磁随机存取存储器（STT-MRAM）单元的存储单元阵列和通常连接到多个STT-MRAM单元的源极线。 源极线电压发生器响应于外部电源电压产生源极线驱动电压，并将源极线驱动电压提供给源极线。

公开(公告)号：US07782688B2

公开(公告)日：2010-08-24

申请号：US12004715

申请日：2007-12-21

申请人： Yong-Jun Kim ,  Woo-Seop Jeong ,  Kyu-Chan Lee

发明人： Yong-Jun Kim ,  Woo-Seop Jeong ,  Kyu-Chan Lee

IPC分类号： G11C7/00

CPC分类号： G11C29/56 ,  G01R31/318511 ,  G11C29/006 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/5602 ,  H01L2224/06156

摘要： Provided are a semiconductor memory device and a test method thereof. The semiconductor memory device includes: a die in which a plurality of internal circuits are integrated; a plurality of first and second channel pads having a first pad size and a first pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows, wherein the plurality of first and second channel pads are configured to selectively contact test probes in an alternating manner to receive an external wafer test signal and to output a signal generated by the plurality of internal circuits to the exterior. Therefore, it is possible to perform a test using plural channel pads during a wafer test of the semiconductor memory device using a plurality of probes of a probe card without incorrect contacts or non-contact with adjacent pads.

摘要翻译： 提供半导体存储器件及其测试方法。 半导体存储器件包括：集成有多个内部电路的管芯; 具有第一焊盘尺寸和第一焊盘间距的多个第一和第二通道焊盘，以交替的方式设置在模具的中心部分处的直线上，并且被分成多个平行的行，其中多个第一焊盘 并且第二通道焊盘被配置为以交替方式选择性地接触测试探针以接收外部晶片测试信号并将由多个内部电路产生的信号输出到外部。 因此，可以在半导体存储器件的晶片测试期间使用多个探针卡的探针来进行使用多个通道焊盘的测试，而不会与相邻的焊盘不接触或不接触。

公开(公告)号：US20080298111A1

公开(公告)日：2008-12-04

申请号：US12079995

申请日：2008-03-31

申请人： Hyo-Joo Ahn ,  Kyu-Chan Lee ,  Chul-Woo Yi

发明人： Hyo-Joo Ahn ,  Kyu-Chan Lee ,  Chul-Woo Yi

IPC分类号： G11C5/02 ,  G11C7/00

CPC分类号： G11C5/025 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/11898

摘要： A semiconductor memory device includes: a substrate with first and second memory-cell array regions disposed on first and second substrate sides and first and second sense-circuit regions disposed on the first and second substrate sides between the first and second memory-cell array regions; first and second bitlines coupled to a plurality of memory cells in the first memory-cell array region; first and second complementary bitlines coupled to a plurality of memory cells in the second memory-cell array region; first and second column-selection transistors formed in the first sense-circuit region, and selectively couple the first bitline and the first complementary bitline to a first input/output (I/O) line and a first complementary I/O line; and third and fourth column-selection transistors formed in the second sense-circuit region, and selectively couple the second bitline and the second complementary bitline to a second I/O line and a second complementary I/O line.

摘要翻译： 半导体存储器件包括：具有设置在第一和第二衬底侧上的第一和第二存储单元阵列区域的衬底以及设置在第一和第二衬底侧的第一和第二存储单元阵列区域之间的第一和第二感测电路区域 ; 第一和第二位线耦合到第一存储单元阵列区域中的多个存储单元; 第一和第二互补位线耦合到第二存储单元阵列区域中的多个存储单元; 形成在第一感测电路区域中的第一和第二列选择晶体管，并且将第一位线和第一互补位线选择性地耦合到第一输入/输出（I / O）线和第一互补I / O线; 以及形成在第二感测电路区域中的第三和第四列选择晶体管，并且选择性地将第二位线和第二互补位线耦合到第二I / O线和第二互补I / O线。

公开(公告)号：US20080259668A1

公开(公告)日：2008-10-23

申请号：US12078724

申请日：2008-04-03

申请人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

发明人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

IPC分类号： G11C5/02 ,  G11C7/06

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

摘要翻译： 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。